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Carey Robertson: Reliability Checks in Advanced Nodes

Carey Robertson: Reliability Checks in Advanced Nodes
by Daniel Nenni on 04-28-2014 at 8:30 pm

Last week I had the pleasure of presenting at the Electronic Design Process Symposium (EDPS) workshop. This was my first time attending and I was very impressed. There were good presentations but I learned as much from the Q&A and the side conversations before/after/breakfast/lunch/etc. If you have the opportunity to attend, I would highly encourage anyone in the design or EDA community to attend.

 My presentation slides can be found here:

http://www.eda.org/edps/Papers/5-2%20Carey%20Roberston.pdf

The second day of the Symposium was dedicated to IP and I presented in the IP Verification and Reliability track. As everyone knows, reliability is not specific to a particular node nor is it confined to a particular application area. The overall need or requirement may be different from 130nm to 16/14nm or for an automotive application vs. a smart phone application but every designer has certain constraints and methodologies that are utilized to prevent electrical failure. To meet this need, we developed Calibre PERC (Programmable Electrical Rule Checking) and we have developed a number of solutions that allow designers to verify that their designs are robust against Electrostatic Discharge (ESD) events, Electrical Overstress (EOS) conditions, Latch-Up, Power Domain Verification, and Voltage-Aware DRC checks. These are common reliability concerns for circuit designers that, without PERC, forced designers to over-design or employ manual methods for verification. PERC automates this verification ensuring circuit robustness.

These checks and methodologies have been available to the full-chip designer and recently we have partnered with foundries to make them available to IP designers as well. Recently, we announced a collaboration with TSMChttp://www.mentor.com/company/news/mentor-tsmc-calibre-perc where PERC checks have been integrated into the TSMC 9000 program so that IP vendors can leverage the infrastructure developed by Mentor Graphics and TSMC; and run this verification on IP cells/blocks before delivery to the end customer. These are the same checks run at full-chip but categorized so that the IP provider utilizes the specific reliability checks that are appropriate for that circuit.

The “kit” where these checks reside is called the ESD/Latch-up kit and the verification is focused on that particular electrical problem. Some questions were inquiries as to what checks will come next. As I mentioned, with PERC, we have offerings for EOS, Electromigration, etc. What comes next will be largely determined by designers and what they determine is the next problem we should tackle. There have been a lot of articles published about Electromigration needs especially at advanced nodes. EOS is also a hot topic. I would like to pose the question here and see what you think is the most pressing need for circuit reliability……

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