Analyzing Clocks at 7nm and Smaller Nodes

In the good old days the clock signal looked like a square wave , and had a voltage swing of 5 volts, however with 7nm technology the clock signals can now look more like a sawtooth signal and may not actually reach the full Vdd value of 0.65V inside the core of a chip. I’ll cover some of the semiconductor market trends, and then challenges of analyzing high performance clocks at 7nm and smaller process nodes.

Market Trends

Foundries like TSMC, Samsung and Intel are offering 7nm technology to designers working on a wide array of SoC devices that are used in: AI, robotics, autonomous vehicles, avionics, medical electronics, data centers, 5G networks and mobile devices. These designs demand high integration in the billion transistor range, and low power to operate on batteries or within a strict power budget.

7nm Design Challenges

There are plenty of design challenges with advanced nodes, like:

• Transistor aging effects
• Higher design costs, in the range of $120-$420 million per 7nm design
• Reduced design margins with lower Vdd levels
• Power consumption rising with clock frequency
• Process variation effects
• Larger delay variations
• Interconnect RC variation increases
• Higher resistance interconnect causing signal distortions
• Larger power transients from faster transistor switching times
• Many more clocks with multi-voltage power domains
• An increase in power density and chip temperatures related to switching
• Dramatic increase in the DRC rule deck complexity

Aging Effects

As transistor devices switch on and off there are two main physical effects that impact the reliability:

• Negative Bias Temperature Instability (NBTI)
• Hot Carrier Injection (HCI)

Circuit designers learn that these aging effects change the Vt of devices, which in turn will slow down the rise and fall times of the clock signals.  These aging effects over time will distort the duty cycle of the clock, and can actually cause the clock circuitry to fail. Shown below are two charts where the clock Insertion Delay and Duty Cycle eventually fail, caused by aging effects. The increase in clock jitter and rail to rail (R2R) violations also appear as aging effects.

Static Timing Analysis (STA) 

For many years, EDA users have relied upon STA tools, however these tools make simplifying assumptions about aging effects by applying a blanket timing derating, instead of applying aging based upon actual switching activity. The interconnect delay model in STA will miss duty cycle distortion errors in long signal nets due to resistive shielding. A STA tool also doesn’t catch rail-to-rail failures directly, although it does measure insertion delays and slew rates. Jitter isn’t simulated as part of a STA tool, so the designer doesn’t know which areas have highest noise that require fixing.

Overcoming Analysis Limitations

An ideal clock analysis methodology would provide SPICE-level accuracy of an entire clock domain, even with millions of devices. It would allow an engineer to measure R2R and jitter at every node along the entire clock path, both with and without aging. Multiple clocks could be analyzed across many process corners and Vdd combinations, working from within the current EDA tool flow, and produce results overnight.

Infinisim Approach

Infinisim is an EDA vendor that has focused on clock analysis, and their tool is called ClockEdge. Here are two analysis examples of clock domain rise slew rate, and clock domain aged insertion delay from their tool:

CAD developers at Infinisim figured out how to simulate the entire clock domain, producing full analog results with SPICE accuracy, allowing SoC teams to actually measure the clock duty cycle while aging, or measure R2R, even measure noise-induce jitter. The ClockEdge tool even runs in a distributed fashion across multiple servers in order to produce results overnight.

ClockEdge really complements STA, so continue to use both tools, where ClockEdge becomes your clock sign-off tool. All of the device aging models are supplied by your foundry. As an example of the performance of ClockEdge, it has been run on a clock circuit with 4.5 million gates, containing billions of transistors; trace required 4.5 hours, and simulation was 12 hours total time, running on 250 CPUs.

Summary

Designing an SoC at 7nm and smaller process node is a big task, requiring specialized knowledge of clock analysis to ensure first-pass silicon success. Adding a new tool like ClockEdge into your EDA tool flow is a smart step to mitigate the effects of device aging and other effects.

Related Blogs

• White Paper: A Closer Look at Aging on Clock Networks