Verific Sharpening the Saw

Verific is an unusual company. They are completely dominant in what they do – providing parsers for Verilog/SV, VHDL and UPF. Yet they have no ambition to expand beyond that goal. Instead, per Michiel Ligthart (President and COO), they continue to “sharpen the saw”. This is an expression I learned in sales training, habit #7 from 7 Habits of Highly Effective People. Constantly refining and polishing (or sharpening) the tools you already have rather than launching out into building new tools. That’s a great way to keep existing customers loyal and to steadily grow a business. They are still investing in interesting development, but it is all around these core tools.

The Core Business

Michiel told me that their SystemVerilog continues very strong, as does VHDL. A blow perhaps for those who hope VHDL is approaching its end. Apparently this is partly a function of popular IPs available only in VHDL and partly a function of markets or organizations which are still VHDL-centric (think defense, aerospace, FPGA).

Speaking of markets, Verific continues strong with all the major and many of the minor EDA vendors. It also continues to enjoy popularity among semi and systems development groups in support of utility applications – glue, proprietary transforms, analytics and other functions. Michiel mentioned that demand for their UPF parser was originally low but has been picking up recently. I would guess the slow start probably reflects EDA vendors wanting to keep UPF parsing in-house for now. Recent pickup in demand then reflects designs teams extending to analysis and manipulation of UPF for their own purposes.

Michiel acknowledged that they continue to polish for corner cases (I remember this was a constant battle in Atrenta.) Verific may not be perfect (even the standards aren’t perfect) but they continue to pursue that goal as their priority.

Beyond the Basics: Cross Module References

Support for these is good example of sharpening the saw with a little new development. Cross module references (XMRs) are those references you can embed in your RTL like top.A.B.x. XMRs are essential for assertions and more generally for verification/debug. I can even imagine them being useful for quick what-if experiments within functional code, without having to go through the pain of making a change synthesis-legal.

It turns out that handling XMRs efficiently in a parser is trickier than it might appear. The logic for a simulator is easy enough, but uniquification can blow memory consumption up massively. Now Verific is finishing up an improved data structure  to better support path-based uniquification which can dramatically limit this growth.

Scripting in Python

This one should attract a lot of attention – it certainly has among system clients. EDA vendors and CAD teams want to work with Verific at the C++ level, but that only makes sense when developing or extending tools that will have a wide audience and be needed for many years. Design groups have always needed utilities to manipulate design content for a smaller audience and likely smaller half-life. They need scripting capabilities and the scripting language of choice these days is Python which is nicely reflected in Verific’s INVIO add-on to its parsers (Sorry Tcl fans. You are strong in implementation, but you have no play in pure RTL manipulation.) I predict Python manipulation of SV, VHDL and UPF is likely to attract a very eager following.

In short, Michiel and team continue to sharpen the saw in interesting ways, but with a continued focus on keeping loyal customers happy above all. You can learn more about Verific HERE.

Also read:

COO Interview: Michiel Ligthart of Verific

2021 Retrospective. Innovation in Verification

Topics for Innovation in Verification