Configurable System IP from a Tool Provider

While I have previously blogged on Forte’s Cynthesizer Workbench’s Interface Generator, I want to take another look from a different perspective. Watching the tool and IP together in action through public videos provided by Forte it struck me as odd what I did not consider earlier, on what should have been obvious to me – Forte is not only providing a tool, they are providing validated IP. We expect to see semiconductor intellectual property (SIP) coming from a SIP company such as ARM or Sonics, or from one of the big EDA companies in that market, such as Cadence or Synopsys. But, we do not often see SIP coming from a tool company that is not one of the Big 3.

Why is this important? It is important because one of the best techniques a designer has in improving their productivity is in design reuse and the use of pre-verified SIP. I just wrote a piece about this in another article about the concerns from Bill Dally of nVidia on the need to improve design productivity. Dally laments the time a couple guys could design a chip in a few weeks, a process today that takes 6 months or usually much more. It would seem the key components to get there are to raise the level of abstraction, to dramatically increase the amount of reusable IP, and to adopt a network-on-chip (NoC) architecture to connect the blocks all together. While Dally took this so far as to imply more reusable hard IP, a lot can be gain from pre-verified soft IP if the designers would just stop editing it. It is already verified, so simply leave it alone and take the productivity gains rather than risk the schedule delays and potential bug introductions from trying to improve it.

Another point is to look at the type of IP that Forte is providing – Interface IP. This is in contrast to Forte’s former competitor Synfora whose assets were bought cheaply by Synopsys a bit more than three years ago. Synfora was also a high-level synthesis (HLS) provider which spun-out of Hewlett-Packard. Initially, the company was developing an HLS tool which was tightly coupled with a proprietary processor. That turned out to be a very hard sell. Interface IP provides functions which most every chip can use in different styles of implementation such as point-to-point or FIFO. But a processor is more closely tied to the overall performance of the design and the designers tend to be very familiar with how to use it. The approach Synfora was taking was more like competing with ARM except ARM had a much better ecosystem around its processors. Synfora later abandoned this approach though perhaps too late since a lot of money was burned along the way. In contrast, Forte’s is providing IP to solve problems that come up often but fall into an area where differentiation is not needed. Forte got it right.

To see an example of the Forte Interface IP in action watch the video on their website. The video is well done and runs less than 12 minutes. It should be well worth your time.

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