Jasper Asian Seminars

Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.

This full-day tutorial will be given by technical experts for verification experts and will cover, among other things:

• Formal verification of RTL blocks
• Debug and design exploration
• Post-silicon debug and root cause analysis
• Verification of ARM-protocol based SoCs (AXI, AMBA, AHB, ACE)
• Verification of SoCs with complex memory sub-systems (DDRxx)
• Verification of designs including power-management structures
• SoC and IP connectivity
• Control status registers
• Closure and coverage
• Clock domain crossing
• X-propagation

May 15 Hsinchu Taiwan
Sheraton Hotel
No. 265, Dong Sec. 1,
Guangming 6th Rd
Zhubei City 302
To register for this seminar contact Kay Lan at phone: 866-3-5739968 x21 email kay@kaviaztech.com

May 17 Beijing, China
Park Plaza Hotel
No. 25, Zhichun Road
Haidian District
Beijing
To register for this seminar contact 8610.8280-0729 ext. 8001 email bingfeng@ops-eda.com

May 18 Shanghai, China
Parkyard Hotel
No. 699, Bibo Road
Zhangjiang District
Shanghai
To register for this seminar contact 8610.8280-0729 ext. 8001 email bingfeng@ops-eda.com

Details of the seminars in Chinese are here.