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IP

Semiconductor Intellectual Property

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Controlling the Automotive Network – CAN and TSN Update

Controlling the Automotive Network – CAN and TSN Update
by Bernard Murphy on 08-18-2021 at 6:00 am
Categories: Automotive, Avery Design Systems, IP

automotive networks

Cars are hotbeds of systems innovation. I’ve been fortunate to be asked to write about many of these areas, from the MEMS underlying sensors to ISPs and radars, intelligent imaging and sensor fusion. And many aspects of design for safety within the SoCs around a car. But I haven’t written much about the networks connecting these … Read More

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Synopsys’ Complete 800G Ethernet Solutions

Synopsys’ Complete 800G Ethernet Solutions
by Kalar Rajendiran on 08-12-2021 at 10:00 am
Categories: IP, Synopsys

Evolution of Ethernet Speeds

If I ask the question, “What has grown 4,000x over the last twenty-five years?”, most people will start throwing names of some stocks. Although various stock markets have had crazy run ups and yes, there is a stock that has grown 2,500x over that period of time, the answer to the 4,000x question is not a stock. What if I modify the question… Read More

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Quantum Computing and Threats to Secure Communication

Quantum Computing and Threats to Secure Communication
by Kalar Rajendiran on 08-09-2021 at 6:00 am
Categories: Intrinsic ID, IP, Security

Our Panelists

There is never a dearth of new terms, discoveries and inventions in the technological world. And sometimes existing terms get reinvigorated. And debates ensue. The debaters argue about the plusses and minuses and make some predictions. Such is the case with “Quantum Computing.” I recently watched and listened to a webinar that… Read More

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An FPGA-Based Solution for a Graph Neural Network (GNN) Accelerator

An FPGA-Based Solution for a Graph Neural Network (GNN) Accelerator
by Kalar Rajendiran on 08-03-2021 at 6:00 am
Categories: Achronix, eFPGA, IP
1 Comment

Screen Shot 2021 07 27 at 9.16.36 PM

Earlier this year, Achronix made a product announcement about shipping the industry’s highest performance Speedster7t FPGA devices. The press release included lot of details about the architecture and features of the device and how that family of devices is well suited to satisfy the demands of the artificial intelligence … Read More

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WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library

WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library
by Daniel Nenni on 07-26-2021 at 6:00 am
Categories: Events, IP, Mirabilis Design, RISC-V

Aug5 TechTalk 2

80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design.  RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities.  Can it really attain the utopian success that people are looking… Read More

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Architecture Exploration with Miribalis Design

Architecture Exploration with Miribalis Design
by Deepak Shankar on 07-23-2021 at 6:00 am
Categories: IP, Mirabilis Design

AE1

Architectural exploration is a vast area of engineering design. It starts with the planning phase where the designer will have the list of requirements from the customer and the rough architecture most likely on a paper. Next is to assemble the model and conduct variety of trade-offs for optimization and functional studies to … Read More

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A Hardware Security Standard Advances

A Hardware Security Standard Advances
by Bernard Murphy on 07-21-2021 at 6:00 am
Categories: Accellera, IP, Security

security min

Security is a slippery topic. We all agree that “something should be done”, but most of us are waiting for someone else to lead the way. There’s no shortage of proprietary solutions, though given the distributed nature of the problem it’s difficult to see how those separately or collectively can rise to the occasion. What we really… Read More

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Cadence Tensilica FloatingPoint DSPs

Cadence Tensilica FloatingPoint DSPs
by Kalar Rajendiran on 07-15-2021 at 10:00 am
Categories: Cadence, IP

Tensilica FP DSPs

Being engrossed in the digital information world, it is easy to forget that the real world is comprised of mostly analog signals and data. Digital Signal Processors (DSP) take digitized forms of these worldly signals and manipulate them mathematically. Although floating-point is a more relevant and accurate way of representing… Read More

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StarFive Surpasses Development Goal with the Prodigy Rapid Prototyping System from S2C

StarFive Surpasses Development Goal with the Prodigy Rapid Prototyping System from S2C
by rdgreen on 07-13-2021 at 10:00 am
Categories: EDA, Prototyping, RISC-V, S2C EDA

SartFive

Faced with the challenge of developing a high-performance hardware platform with critical software components, what choices do companies have in rapidly moving their development forward with modest budgets and resources?

That was the challenge faced by StarFive Technology, a leading IP and semiconductor SoC platform solution… Read More

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PCIe Gen 6 Verification IP Speeds Up Chip Development

PCIe Gen 6 Verification IP Speeds Up Chip Development
by Tom Simon on 07-08-2021 at 10:00 am
Categories: IP, Truechip

PCIe Gen 6 VIP

PCIe is a prevalent and popular interface standard that is used in just about every digital electronic system. It is used widely in SOCs and in devices that connect to them. Since it was first released in 2003, it has evolved to keep up with rapidly accelerating needs for high speed data transfers. Each version has doubled in throughput,… Read More