SILVACO 073125 Webinar 800x100
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Fail-Safe Electronics For Automotive

Fail-Safe Electronics For Automotive
by Kalar Rajendiran on 12-27-2023 at 10:00 am

MegaTrends Driving the Need for Next Generation Silicon Capabilites

The automotive industry is on the brink of a revolutionary transformation, where predictive maintenance and monitoring are taking center stage. In a recent webinar panel session, industry experts delved into the challenges, current approaches, and future innovations surrounding the guarantee and extension of mission profiles.… Read More


Agile Analog Partners with sureCore for Quantum Computing

Agile Analog Partners with sureCore for Quantum Computing
by Daniel Nenni on 12-21-2023 at 10:00 am

Agile Analog sureCore project PR image

Quantum computing is the next big thing for the computing world. The semiconductor industry has been talking about it for years. It’s shiny, mysterious, and capable of some incredible things. Instead of using classical bits to represent information (which can be either a 0 or a 1), quantum computers use quantum bits or qubitsRead More


ReRAM Integration in BCD Process Revolutionizes Power Management Semiconductor Design

ReRAM Integration in BCD Process Revolutionizes Power Management Semiconductor Design
by Kalar Rajendiran on 12-20-2023 at 10:00 am

Power Analog ICs Adopting ReRAM

Weebit Nano, a leading developer of advanced memory technologies, recently announced a significant collaboration with DB HiTek, one of the top ten foundries of the world. The collaboration is designed to enable integration of Weebit’s Resistive Random-Access Memory (ReRAM) into DB HiTek’s 130nm Bipolar-CMOS-DMOS… Read More


RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation

RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation
by Mike Gianfagna on 12-19-2023 at 8:00 am

RISC V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation

One of the goals of the recent RISC-V Summit was to demonstrate that the RISC-V movement is real – major programs by large organizations committing to development around the RISC-V ISA. I would say this goal was achieved. Many high-profile announcements and aggressive, new architectures based on RISC-V were presented. On day … Read More


Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure

Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure
by Kalar Rajendiran on 12-19-2023 at 6:00 am

Alphawave Semi 224G SerDes 1st TestChip

In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More


Ceva Launches New Brand Identity Reflecting its Focus on Smart Edge IP Innovation

Ceva Launches New Brand Identity Reflecting its Focus on Smart Edge IP Innovation
by Daniel Nenni on 12-18-2023 at 10:00 am

New CEVA Logo
Company sharpens its strategy of delivering silicon and software IP that makes it possible for low power Edge AI devices to connect, sense and infer data, reliably and efficiently, across multiple high-growth end markets

Ceva Inc. is an interesting company. Founded in November 2002, through the combination of the DSP IP licensing… Read More


RISC-V and Chiplets: A Panel Discussion

RISC-V and Chiplets: A Panel Discussion
by Paul McLellan on 12-13-2023 at 10:00 am

rvnames

At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:

  • Laurent Moll, COO of Arteris
  • Aniket Saha, VP of Product Management of Tenstorrent
  • Dale Greenley, VP of Engineering of Ventana
Read More

When Will Structured Assembly Cross the Chasm?

When Will Structured Assembly Cross the Chasm?
by Bernard Murphy on 12-13-2023 at 6:00 am

Trends in assembly min

First, a quick definition. By “structured assembly,” I mean the collection of tools to support IP packaging with standardized interfaces, SoC integration based on those IPs together with bus fabric and other connectivity hookups, register definition and management in support of hardware/software interface definition, Read More


Automated Constraints Promotion Methodology for IP to Complex SoC Designs

Automated Constraints Promotion Methodology for IP to Complex SoC Designs
by Kalar Rajendiran on 12-12-2023 at 6:00 am

Synopsys Timing Constraints Manager

In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that… Read More


UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
by Kalar Rajendiran on 12-11-2023 at 6:00 am

Pike Creek UCIe Test chip

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More