You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today!
WP_Term Object
(
[term_id] => 178
[name] => IP
[slug] => ip
[term_group] => 0
[term_taxonomy_id] => 178
[taxonomy] => category
[description] => Semiconductor Intellectual Property
[parent] => 0
[count] => 1778
[filter] => raw
[cat_ID] => 178
[category_count] => 1778
[category_description] => Semiconductor Intellectual Property
[cat_name] => IP
[category_nicename] => ip
[category_parent] => 0
[is_post] =>
)
You have probably already seen the news: Cadence is acquiring Tensilica for $380M. Cadence has been relatively late to the IP party compared to Synopsys. In contrast, Mentor was early, got into the IP business before it was really profitable and ended up shutting down the business.
Tensilica is quite sizable. It has over 200 licensees,… Read More
At a different time, but certainly within the past 12 months, Paul Otellini was asked if Intel would be a Foundry for Qualcomm. His reply was that it did not leave a good taste in his mouth. Nevertheless it was not rejected and the door that remained open just a crack is likely to swing open for Qualcomm, the premier mobile silicon supplier… Read More
We have frequently said in Semiwiki how crucial is it for the SC industry to benefit from high quality PHY IP… even if, from a pure business point of view (MBA minded), PHY IP business does not look so attractive. In fact, to be able to design on-the-edge SerDes and PLL (the two key pieces), you need to build and maintain a highly skilled… Read More
Embedded NVM technology based functions can be implemented in large SoC designed in advanced technology nodes down to 28nm, as there is no requirement for extra mask levels, like when integrating Nand Flash, negatively impacting the final cost. And it is also possible to integrate One Time Programmable (OTP) to store trim and … Read More
Like Guiness dark beer, competition is good for you! I mean good for end user, as it pushes DSP IP supplier to provide ever better solution. I am not talking about me-to type of competition, like that we have seen in the past with IBM trying to displace TI at Nokia, by offering a LEAD (DSP IP core from TI used in every NOKIA wireless phone… Read More
The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively.… Read More
I have blogged in 2011 about the Arteris-Sonics case, initiated by Sonics, claiming that Arteris NoC IP product was infringing Sonics patent. In this article, we have seen that the architecture of Sonics interconnects IP product was not only older but also different from Arteris’ NoC architecture: the products launched initially… Read More
One of the privilages of blogging for SemiWiki is invitations to the top conferences around the world including the International Solid-State Circuits Conference (ISSCC) in San Francisco this week. Amazing, this conference is older than I am:
ISSCC 2013 is the 60th Conference in an incredibly long-lasting series. Following… Read More
(with apologies to George Harrison) Two recent Blogs over at ReRAM-Forum.com have focused on the latest in the IP field, particularly as it affects resistive memory. A high level overview of who is patenting what suggests a healthy amount of R&D is going on in the field. But looking a little deeper suggests there is much overlap… Read More
You are going to be developing software for an SoC that contains an ARM Cortex-A57 64-bit CPU. Or perhaps it is an SoC containing ARM’s hybrid big.LITTLE multi-core architecture that combines one or more low power cores with some high power, high performance cores to get the best of both worlds: high throughput when it is needed… Read More
Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?