Of all the live events I attend ARM TechCon is one of my favorites. The keynotes are always very good but the real meat of the conference is who attends because that is who the content is specifically developed for:… Read More
Semiconductor Intellectual Property
Why Gemini 2.0 is tailored for tomorrow’ SoC designs?
You probably have seen many times this graphic showing that the number of IP blocks has exploded, going from a few dozens in SoC designed in 65 nm to 120 if not more for last generation SoC targeting 16FF or 10FF. This graphic is very good at synthesizing the raw IP count, but it doesn’t tell you about another strong trend: more agents … Read More
Is This a Dagger Which I See Before Me?
Macbeth may have been uncertain of what he saw but, until recently, image recognition systems would have fared even less well. The energy and innovation put into increasingly complex algorithms always seemed to fall short of what any animal (including us humans) is able to do without effort. Machine vision algorithms have especially… Read More
New CoreLink IP ties in mobile GPU coherently
A mobile GPU is an expensive piece of SoC real estate in terms of footprint and power consumption, but critical to meeting user experience demands. GPU IP tuned for OpenGL ES is now a staple in high performance mobile devices, rendering polygons with shading and texture compression at impressive speeds.
Creative minds in the desktop… Read More
Shifting Low Power Verification to an IP to SoC Flow
One of the most exciting recent developments in low power design and verification is the successive refinement flow developed by ARM® and Mentor Graphics®.… Read More
Do 8 Cores Really Matter in Smartphones?
As the smartphone industry has begun to mature, one-upmanship among smartphone manufacturers and SoC vendors has bred a dangerous trend: ever-increasing processor core counts and the association between increased CPU core count and greater performance. This association originated as SoC vendors and OEMs have tried to find… Read More
To err is runtime; to manage, NoC
Software abstraction is a huge benefit of a network-on-chip (NoC), but with flexibility comes the potential for runtime errors. Improper addresses and illegal commands can generate unexpected behavior. Timeouts can occur on congested paths. Security violations can arise from oblivious or malicious access attempts.
Runtime… Read More
How to Make Smartphone Even Smarter? With Deep Learning
The IT industry marvels like augmented reality and artificial intelligence, which marked technological utopianism in the science fiction movies during the 1970s and 1980s, are here now, enabled by a machine-learning technique called deep learning.… Read More
Eliminating the Chasm of Computing
The world has come through a long way from the 1[SUP]st[/SUP] UNIVAC computer in 1952, IBM mainframes and minicomputers in secured computer rooms to laptops, tablets, mobile phones, and so on in our hands. Imagine the compute power of a minicomputer then and the compute power of your smartphone or tablet today. And do you know the… Read More
Interconnect Watch: 3 Chip Design Merits for Network Applications
The countdown to the end of Moore’s Law is coinciding with the rising complexity in system-on-chip (SoC) designs. And that’s not a mere coincidence. The leverage that has long been coming from shrinking process nodes in terms of cost, performance and power benefits is now increasingly being accomplished through… Read More
Quantum Advantage is About the Algorithm, not the Computer