Events EDA2025 esig 2024 800X100
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eFPGA
Posted on

Fast Track to a reconfigurable ASIC design

Fast Track to a reconfigurable ASIC design
by Don Dingee on 04-25-2016 at 4:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP

Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More

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TSMC and Flex Logix?

TSMC and Flex Logix?
by Daniel Nenni on 03-26-2016 at 7:00 am
Categories: eFPGA, Events, Flex Logix, IP, TSMC

There was a lot to learn at the TSMC Technical Symposium last week, in the keynotes for sure but also in the halls and exhibits. Tom Dillinger did a nice job covering the keynotes in his posts Key Take aways from the TSMC Technology Symposium Part 1 and Part 2 but there was something interesting that many people may have missed in the exhibit… Read More

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Creating a better embedded FPGA IP product

Creating a better embedded FPGA IP product
by Don Dingee on 03-09-2016 at 4:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP

Our introduction to Flex Logix and its embedded FPGA core IP drew several comments, predominantly along the lines of a few things like this have been tried before. In this installment, we dive into the EFLX cores, the FPGA toolchain, the roadmap, and a powerful integration feature.… Read More

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Reconfigurable redefined with embedded FPGA core IP

Reconfigurable redefined with embedded FPGA core IP
by Don Dingee on 02-12-2016 at 7:00 am
Categories: eFPGA, Flex Logix, FPGA, IP

On November 1, 1985, before anyone had heard the phrase field programmable gate array, Xilinx introduced what they called a “new class of ASIC” – the XC2064, with a whopping 1200 gates. Reconfigurable computing was born and thrived around the RAM-based FPGA, whose logic and input/output pins could be architected into a variety… Read More