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Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.
Accuracy is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several… Read More
What was the first EDA company name that came to your mind after reading that title?
At Forbes magazine they rated both Mentor Graphics and Synopsys in the top 25 best companies for work life balance.
That’s quite an honor for both Mentor and Synopsys so I can say that EDA dominated the list this year.
Here are some of the factors… Read More
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
I met with Jeff Wilson, Product Marketing Manager at Mentor in the Calibre product group to learn more about Smart Fill versus Dummy Fill for DFM flows. Jeff works in the Wilsonville, Oregon office and we first meet at Silicon Compilers back in the 1990’s.
Dummy Fill
This diagram shows an IC layout layer on the left as originally… Read More
Workshops are a great where to learn hands-on about IC design technology. Mentor has a free workshop to introduce you to creating, simulating and verifying mixed-signal (Analog and Digital) designs.
PLL waveforms showing both digital and analog signals.
Dates in Fremont, California
July 26, 2011
September 15, 2011
November… Read More
Introduction
Before DAC I met with Stephen Pateras, Ph.D. at Mentor Graphics, he is the Product Marketing Director in the Silicon Test Solutions group. Stephen has been at Mentor for two years and was part of the LogicVision acquisition. He was in early at LogicVision and went through their IPO, before that he was at IBM in the mainframe… Read More
With the adoption of the 32/28 nm process node, some significant new challenges in digital routing arise—including complex design rule checking (DRC) and design for manufacturing (DFM) rules, increasing rule counts, very large (1 billion transistor) designs. To meet quality, time-to-market, and cost targets, design teams… Read More
Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what’s new at DAC this year in circuit simulation and IC layout tools.
Notes
IC Station – old name for IC layout tools
Eldo – Eldo Classic- Cell characterization
– ST is the early customer and teaching customer,… Read More
I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.
Intro
Physware – served the package and board markets, co-design challenges (can add IC noise sources).… Read More
Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:
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[_useReplaceInto:protected] =>
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[navigation_id] =>
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[_relations:protected] => Array
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)
[_previousValues:protected] => Array
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[_options:protected] => Array
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[_deleted:protected] =>
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[_cascadeSave:protected] => Array
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[_deleted:protected] =>
[_readOnly:protected] =>
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[_whenSaveable:protected] => Array
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[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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[populated:protected] => 1
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