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Q2FY24TessentAI 800X100
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ARM and Mentor Team Up on Test

ARM and Mentor Team Up on Test
by Daniel Payne on 06-27-2011 at 2:31 pm

Introduction
Before DAC I met with Stephen Pateras, Ph.D. at Mentor Graphics, he is the Product Marketing Director in the Silicon Test Solutions group. Stephen has been at Mentor for two years and was part of the LogicVision acquisition. He was in early at LogicVision and went through their IPO, before that he was at IBM in the mainframe… Read More


Can Your Router Handle 28 nm?

Can Your Router Handle 28 nm?
by Beth Martin on 06-20-2011 at 7:11 pm

attachment

With the adoption of the 32/28 nm process node, some significant new challenges in digital routing arise—including complex design rule checking (DRC) and design for manufacturing (DFM) rules, increasing rule counts, very large (1 billion transistor) designs. To meet quality, time-to-market, and cost targets, design teams… Read More


Circuit Simulation and IC Layout update from Mentor at DAC

Circuit Simulation and IC Layout update from Mentor at DAC
by Daniel Payne on 06-17-2011 at 7:06 pm

Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what’s new at DAC this year in circuit simulation and IC layout tools.

Notes
IC Station – old name for IC layout tools

Eldo – Eldo Classic- Cell characterization
– ST is the early customer and teaching customer,… Read More


Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop

Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop
by Daniel Payne on 06-13-2011 at 12:57 pm

I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.

Intro

Physware – served the package and board markets, co-design challenges (can add IC noise sources).… Read More


Shakeup at Mentor Graphics

Shakeup at Mentor Graphics
by Daniel Payne on 05-12-2011 at 12:22 pm

Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:

  • José Maria Alapont, chief executive of the auto parts maker Federal-Mogul
  • Gary Meyers, a director of the chip maker Exar
  • David Schechter, an executive at Mr. Icahn’s investment firm
Read More

Graphical DRC vs Text-based DRC

Graphical DRC vs Text-based DRC
by Daniel Payne on 05-01-2011 at 11:42 am

Introduction
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.

At the 28nm node a typical DRC (Design Rule Check) deck will… Read More


Ivo Bolsens of Xilinx and Crossover Designs

Ivo Bolsens of Xilinx and Crossover Designs
by Paul McLellan on 04-27-2011 at 4:14 pm

I was at Mentor’s u2u (user group) meeting and one of the keynotes was by Ivo Bolsens of Xilinx. The other was by Wally Rhines and is summarized here.

Ivo started off talking analogizing SoCs as the sports-cars of the industry (fast but expensive), and FPGAs as the station wagons (not cool). In fact he even said that when Xilinx… Read More


Wally’s u2u keynote

Wally’s u2u keynote
by Paul McLellan on 04-27-2011 at 3:25 pm

I was at Wally’s u2u (Mentor user group) keynote yesterday. The other keynote was by Ivo Bolsens of Xilinx and is here. He started off by looking at how the semiconductor industry has recovered and silicon area shipments are now back on trend after a pronounced drop in 2009 and revenue has followed. Finally the semiconductor… Read More


Transistor-Level Electrical Rule Checking

Transistor-Level Electrical Rule Checking
by Daniel Payne on 04-20-2011 at 11:19 am

Introduction
Circuit designers work at the transistor level and strive to get the ultimate in performance, layout density or low power by creating crafty circuit topologies in both schematics and layout. Along with this quest comes the daunting task of verifying that all of your rules and best practices about reliability have… Read More


Who Needs a 3D Field Solver for IC Design?

Who Needs a 3D Field Solver for IC Design?
by Daniel Payne on 04-07-2011 at 4:53 pm

Inroduction
In the early days we made paper plots of an IC layout then measured the width and length of interconnect segments with a ruler to add up all of the squares, then multiplied by the resistance per square. It was tedious, error prone and took way too much time, but we were rewarded with accurate parasitic values for our SPICE… Read More