Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many converters per bit for higher accuracy requirements, which increases the size of the chip (and likewise the cost).
Not surprisingly, at small process nodes, the influence of parasitic elements on these sensitive mixed-signal designs is growing, due to the increasing interactions between devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, so accurate parasitic extraction is critical for first silicon success.
Constraints used to lay out a flash ADC are also extremely important, because differential pairs must have symmetrical layouts, identical capacitors must have equal values, and resistors must be matched. For example, if one resistor must be over-etched because of process variation sensitivity, all of the resistors must be over-etched in the same way to ensure that the taps off the resistor ladder are still the correct voltage value. Several guidelines can help improve layout matching.
Designing flash ADCs requires careful tradeoffs between speed, accuracy, and power. Highly accurate parasitic extraction ensures that parasitics will not cause the ADC to behave incorrectly, and that the ADC will still meet all of the design specifications.
New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding, while ensuring the circuitry will work according to the specifications when manufactured.
You can download the complete “Reducing the Need for Guardbanding a Flash ADC Design” whitepaper HERE.
About the Author:
Karen Chow is the Technical Marketing Engineer for Calibre xRC and Calibre xACT 3D at Mentor Graphics in Wilsonville, OR. She has worked on both sides of the EDA industry, designing analog ICs and supporting EDA tool development. Karen has her BSc in electrical engineering from the University of Calgary, and her MBA from Marylhurst University. In her spare time, she enjoys playing music in bands, designing clothing and handbags, and quilting.
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