WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 752
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 752
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
    [is_post] => 
)
            
Q2FY24TessentAI 800X100
WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 752
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 752
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
    [is_post] => 
)

High Frequency Analysis of IC Layouts

High Frequency Analysis of IC Layouts
by Daniel Payne on 10-03-2012 at 12:26 pm

IC designers of passive devices often use empirical approaches to perform High Frequency Analysis (HFA), however there is at least one new approach being offered by Mentor Graphics using a tool flow of:

Read More

Mentor Graphics Update at TSMC 2012 OIP

Mentor Graphics Update at TSMC 2012 OIP
by Daniel Payne on 09-26-2012 at 10:45 am

What
In just 20 days you can get an update on four Mentor Graphics tools as used in the TSMC Open Innovation Platform (OIP). Many EDA and IP companies will be presenting along with Mentor, so it should be informative for fabless design companies in Silicon Valley doing business with TSMC.
Read More


Automating Complex Circuit Checking Tasks

Automating Complex Circuit Checking Tasks
by SStalnaker on 09-20-2012 at 7:24 pm

By Hend Wagieh, Mentor Graphics

At advanced IC technology nodes, circuit designers are now encountering problems such as reduced voltage supply headroom, increased wiring parasitic resistance (Rp) and capacitance (Cp), more restrictive electromigration (EM) rules, latch-up, and electrostatic discharge (ESD) damage,… Read More


Built to last: LTSI, Yocto, and embedded Linux

Built to last: LTSI, Yocto, and embedded Linux
by Don Dingee on 09-06-2012 at 8:30 pm

The open source types say it all the time: open is better when it comes to operating systems. If you’re building something like a server or a phone, with either a flexible configuration or a limited lifetime, an open source operating system like Linux can put a project way ahead.

Linux has always started with a kernel distribution,… Read More


Wiring Harness Design

Wiring Harness Design
by Paul McLellan on 09-04-2012 at 5:18 pm

In 2003 Mentor acquired a company doing wiring harness design. Being a semiconductor guy this wasn’t an area I’d had much to do with. But more than most semiconductor people I expect.

But back when I was an undergraduate, I had worked as a programmer for a subsidiary of Philips called Unicam that made a huge range of spectrometers… Read More


The Need for OASIS in Post-layout IC Databases

The Need for OASIS in Post-layout IC Databases
by Daniel Payne on 08-31-2012 at 7:20 pm

OASIS is a hierarchical IC file format used for IC designs that is gradually replacing GDS II throughout the mask data stages. The compelling reason for using OASIS has always been the reduction of file size, and speed up of processing times through the use of hierarchy and fewer translation steps.

At the 45nm node an actual M1 layer… Read More


A Brief History of Mentor Graphics

A Brief History of Mentor Graphics
by Beth Martin on 08-20-2012 at 11:00 pm

In 1981, Pac-Man was sweeping the nation, the first space shuttle launched, and a small group of engineers in Oregon started not only a new company (Mentor Graphics), but an entirely new industry, electronic design automation (EDA).


Mentor founders Tom Bruggere, Gerry Langeler, and Dave Moffenbeier left Tektronix with a great… Read More


While you’re reading the SoC manual

While you’re reading the SoC manual
by Don Dingee on 08-09-2012 at 8:30 pm

There was a day, not too long ago, when a software developer could be intimate with a processor through understanding its register set. Before coding, developers would reach for a manual, digging through pages and pages of 1s and 0s with defined functions to find how to gain control over the processor and its capability. One bit set… Read More


It Takes a Village: Mentor and ARM Team Up on Test

It Takes a Village: Mentor and ARM Team Up on Test
by Beth Martin on 07-18-2012 at 5:01 pm

Benjamin Franklin, “I didn’t fail the test, I just found 100 ways to do it wrong.” I was reminded of this line during a joint Mentor-ARM seminar yesterday about testing ARM cores and memories. The complexity of testing modern SoC designs at advanced nodes, with multiple integrated ARM cores and other IP, opens up plenty of room for… Read More