The entire field of Artificial Intelligence (AI) has resulted from what is called “first principles thinking”, where problems are re-examined using a complete reassessment of the underlying issues and potential solutions. It is a testament to how effective this can be that AI is being used for a rapidly expanding number of applications… Read More
High-Level Synthesis at the Edge
Custom AI acceleration continues to gather steam. In the cloud, Alibaba has launched its own custom accelerator, following Amazon and Google. Facebook is in the game too and Microsoft has a significant stake in Graphcore. Intel/Mobileye have a strong lock on edge AI in cars and wireless infrastructure builders are adding AI capabilities… Read More
Mentor at DVCON 2020!
Are you ready for the premier conference for functional design and verification of electronic systems?
Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP)… Read More
It’s The Small Stuff That Gets You …
The last session I attended at DesignCon 2020 wasn’t a session at all. Rather it was an interactive discussion with Todd Westerhoff, product manager for electronic board systems at Mentor Graphics. Todd made some observations about the way high-performance PCBs are designed today and perhaps the way they should be designed. … Read More
Bringing Hierarchy to DFT
Hierarchy is nearly universally used in the SoC design process to help manage complexity. Dealing with flat logical or physical designs proved unworkable decades ago. However, there were a few places in the flow where flat tools continued to be used. Mentor lead the pack in the years around 1999 in helping the industry move from … Read More
Formal and High-Level Synthesis
Formal verification has made significant inroads in RTL and gate-level verification because it provides complementary strengths to conventional dynamic verification methods; using both provides higher levels of coverage and confidence in the correctness of an implementation. I haven’t heard as much about formal use in … Read More
Saving Time in Physical Verification by Reusing Metadata
Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:
- Physical validation
- Circuit validation
- Reliability verification
This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More
PAVE360 is Fully Armed!
Siemens today announced a partnership with Arm to “accelerate the future of mobility by redefining design capabilities for complex electronic systems”. I spent time with David Fritz to understand what this really means. You may remember David from our webinar PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle… Read More
Full Solution for eMRAM Coming in 2020
It’s amazing to think that Apollo moon mission used computers that were based on magnetic core memories. Of course, CMOS memories superseded them rapidly. However, over the decades since, memory technologies have advanced significantly, in terms of density, power and new types of technologies, e.g NAND Flash. Ever since the… Read More
A VIP to Accelerate Verification for Hyperscalar Caching
Non-volatile memory (NVM) is finding new roles in datacenters, not currently so much in “cold storage” as a replacement for hard disk drives, but definitely in “warm storage”. Warm storage applications target an increasing number of functions requiring access to databases with much lower latency than is possible through paths… Read More