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Q2FY24TessentAI 800X100
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Achieving Faster Design Verification Closure

Achieving Faster Design Verification Closure
by Daniel Payne on 02-01-2023 at 10:00 am

Questa Verification IQ min

On big chip design projects the logic verification effort can be larger than the design effort, taking up to 70% of the project time based on data from the 2022 Wilson Research Group findings. Sadly, the first silicon success rate has gone downwards from 31 percent to just 24 percent in the past 8 years, causing another spin to correct… Read More


Siemens Aspires to AI in PCB Design

Siemens Aspires to AI in PCB Design
by Bernard Murphy on 12-28-2022 at 6:00 am

PCB min

This. AI in PCB design is not a new idea. Other PCB software companies also make that claim. But when a mainstream systems technology company like Siemens talks about the subject, that is noteworthy. They already have an adaptive user interface (UI) for their mechanical modeling suite and to assist in low-code development for application… Read More


Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward

Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward
by Peter Bennet on 12-22-2022 at 10:00 am

calibre real time digital and custom

You don’t often hear about the inner workings of EDA tools and flows – the marketing guys much prefer telling us about all the exciting things their tools can do rather than the internal plumbing. But this matters for making design flows – and building these has largely been left to the users to sort out. That’s an increasing challenge… Read More


An Update on HLS and HLV

An Update on HLS and HLV
by Daniel Payne on 12-19-2022 at 10:00 am

NCJ29D5 BD2 min

I first heard about High Level Synthesis (HLS) while working in EDA at Viewlogic back in the 1990s, and have kept watch on the trends over the past decades. Earlier this year Siemens EDA hosted a two day event, having speakers from well-known companies share their experiences about using HLS and High Level Verification (HLV) in their… Read More


Cracking post-route Compliance Checking for High-Speed Serial Links with HyperLynx

Cracking post-route Compliance Checking for High-Speed Serial Links with HyperLynx
by Peter Bennet on 12-15-2022 at 6:00 am

hyperlynx flow

SemiWiki readers from a digital IC background might find it surprising that post-PCB route analysis for high speed serial links isn’t a routine and fully automated part of the board design process. For us, the difference between pre- and post-route verification is running a slightly more accurate extraction and adding SI modelling,… Read More


Calibre: Early Design LVS and ERC Checking gets Interesting

Calibre: Early Design LVS and ERC Checking gets Interesting
by Peter Bennet on 11-22-2022 at 6:00 am

fig1

The last thing you want when taping out a design is to hit large numbers of violations in signoff checks that could have been flushed out and resolved in earlier flow iterations. For implementation flows (floorplanning, synthesis, place and route), it’s usual to do a lot of flow flushing work early in the design cycle and iteratively… Read More


Architectural Planning of 3D IC

Architectural Planning of 3D IC
by Daniel Payne on 11-15-2022 at 10:00 am

3D IC min

Before chiplets arrived, it seemed like designing an electronic system was a bit simpler, as a system on chip (SoC) methodology was well understood, and each SoC was mounted inside a package, then the packages for each component were interconnected on a printed circuit board (PCB). The emerging trend to design a 3D IC using chiplets… Read More


Pushing Acceleration to the Edge

Pushing Acceleration to the Edge
by Dave Bursky on 11-04-2022 at 6:00 am

performane table siemens eda

As more AI applications turn to edge computing to reduce latencies, the need for more computational performance at the edge continues to increase. However, commodity compute engines don’t have enough compute power or are too power-hungry to meet the needs of edge systems. Thus, when designing AI accelerators for the edge, Joe… Read More


Why Use PADS Professional Premium for Electronic Design

Why Use PADS Professional Premium for Electronic Design
by Daniel Payne on 11-01-2022 at 6:00 am

PADS Designer min

My IC design career started just a few years before PADS got started in 1985 with a DOS-based tool for PCB design. A lot has changed since then, as PADS was acquired by Mentor Graphics in 2001, and continued to grow under Siemens EDA, now with four versions to choose from, where the top version is called PADS Professional Premium:

  • PADS
Read More

DFT Moves up to 2.5D and 3D IC

DFT Moves up to 2.5D and 3D IC
by Daniel Payne on 10-06-2022 at 10:00 am

2.5D and 3D chiplets min

The annual ITC event was held the last week of September, and I kept reading all of the news highlights from the EDA vendors, as the time spent on the tester can be a major cost and the value to catching defective chips from reaching production is so critical. Chiplets, 2.5D and 3D IC design have caught the attention of the test world, … Read More