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IP Management Using both Git and Methodics

IP Management Using both Git and Methodics
by Daniel Payne on 09-03-2018 at 12:00 pm

I use Quicken to manage my business and personal finances because it saves me so much time by downloading all of my transactions from Chase for credit card, Amazon for credit card, Wells Fargo for banking and Schwab for IRA. Likewise, for IP management in SoC design you want an app like Quicken that plays well with other tools that you… Read More


ISO 26262 Traceability Requirements for Automotive Electronics Design

ISO 26262 Traceability Requirements for Automotive Electronics Design
by Daniel Payne on 06-12-2018 at 12:00 pm

Reading the many articles on SemiWiki and other publications we find experts talking about the automotive market, mostly because it’s in growth mode, has large volumes and vehicles consume more semiconductors every year. OK, that’s on the plus side, but what about functional safety for automotive electronics?… Read More


Combining IP and Product Lifecycle Tools

Combining IP and Product Lifecycle Tools
by Daniel Payne on 04-03-2018 at 12:00 pm

No single EDA company provides all of the tools needed to define requirements, design exploration, track IP, simulate, manage and verify a complex SoC system, so it makes sense that EDA vendors and point tool companies have tools that work together to achieve all of these difficult tasks. Systems design has been around for decades… Read More


SoC Design Management with Git

SoC Design Management with Git
by Daniel Payne on 02-21-2018 at 12:00 pm

Linux creator Linus Torvalds lives in Oregon not too far from me and he also created the popular Git system for Design Management (DM) in 2004 that is now used by many software developers. So what makes Git so attractive as a DM tool?

  • Feature-branch workflow
  • Easy to switch context between features
  • New features can be created orderly
Read More

Hierarchy Applied to Semiconductor IP Reuse

Hierarchy Applied to Semiconductor IP Reuse
by Daniel Payne on 11-30-2017 at 12:00 pm

When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More


Rethinking IP Lifecycle Management

Rethinking IP Lifecycle Management
by Daniel Payne on 10-18-2017 at 12:00 pm

We recently saw both Apple and Samsung introduce new smart phones, and realize that the annual race to introduce sophisticated devices that are attractive and differentiated is highly competitive. If either of these companies misses a market window then fortunes can quickly change. SoCs with billions of transistors like smart… Read More


Something New in IP Lifecycle Management

Something New in IP Lifecycle Management
by Daniel Payne on 07-19-2017 at 12:00 pm

Last month at DAC I met up with Michael Munsey of Methodics to get a quick update on what has been happening over the past 12 months within his company, and he quickly invited me to watch an archived webinar on their latest tool for IP Lifecycle Management called Percipient. I love to play the board game Scrabble, so i had to Google the … Read More


New Concepts in Semiconductor IP Lifecycle Management

New Concepts in Semiconductor IP Lifecycle Management
by Daniel Nenni on 06-27-2017 at 7:00 am

Right before #54DAC I participated in a webinar with Methodics on “New Concepts in Semiconductor IP Lifecycle Management” with Simon Butler, CEO of Methodics, Michael Munsey, Vice President of Business Development and Strategic Accounts, and Vishal Moondhra, Vice President of Applications. Thewebinar introducedRead More


Webinar -New Concepts in Semiconductor IP Lifecycle Management

Webinar -New Concepts in Semiconductor IP Lifecycle Management
by Daniel Payne on 05-26-2017 at 7:00 am

The semiconductor IP market continues growing at a healthy rate, and IP reuse is a staple of all modern SoC designs. Along with the acceptance of IP reuse comes a host of growing challenges, like:

  • Increase in design files
  • Increase in meta-data
  • More links between design members worldwide
  • More links between data in multiple engineering
Read More

Achieving Requirements Traceability from Concept through Design and Test

Achieving Requirements Traceability from Concept through Design and Test
by Daniel Payne on 05-09-2017 at 12:00 pm

Excel is a wonderful, general purpose spreadsheet tool that lets me organize and analyze rows and columns of data into something meaningful, however it doesn’t know anything about requirements traceability for complex semiconductor projects. So why do so many engineering teams still rely upon Excel or custom, in-house… Read More