SILVACO 073125 Webinar 800x100
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Connecting System Design to the Enterprise

Connecting System Design to the Enterprise
by Bernard Murphy on 06-16-2021 at 6:00 am

Connecting System Design to the Enterprise min

While systems design underpins the explosion in “smart everything”, it remains somewhat isolated from another explosion—the proliferation of tools for application lifecycle management (ALM). ALM tools are prevalent on the web, in the cloud and on our phones, to streamline product design and build, to track correspondence… Read More


Keynote from Google at CadenceLIVE Americas 2021

Keynote from Google at CadenceLIVE Americas 2021
by Kalar Rajendiran on 06-14-2021 at 10:00 am

CDNLive Americas 2021

Last week, Cadence hosted its annual CadenceLIVE Americas 2021 conference. Four keynotes and eighty-three different talks on various topics were presented. The talks were delivered by Cadence, its customers and partners.

One of the keynotes was from Partha Ranganathan, VP and Engineering Fellow from Google. His talk was titled,… Read More


Software Developers Turn to CacheQ for Multi-Threading CPU Acceleration

Software Developers Turn to CacheQ for Multi-Threading CPU Acceleration
by Lauro Rizzatti on 06-07-2021 at 10:00 am

image001 6

Three-year old CacheQ, founded by two former Xilinx executives and a clever group of engineers, produces a distributed heterogenous compute development environment targeting software developers with limited knowledge of hardware architecture.

The promise of compiler tools for heterogeneous compute systems intrigued… Read More


RealTime Digital DRC Can Save Time Close to Tapeout

RealTime Digital DRC Can Save Time Close to Tapeout
by Tom Simon on 06-07-2021 at 6:00 am

RealTime DRC

Over the years DRC tools have done an admirable job of keeping pace with the huge growth of IC design size. Yet, DRC runs for sign off on the full design using foundry rule decks take many hours to complete. These long run times are acceptable for final sign off, but there are many situations where DRC results are needed quickly when small… Read More


Speed Up LEF Generation Times on Huge IC Designs

Speed Up LEF Generation Times on Huge IC Designs
by Daniel Payne on 06-03-2021 at 10:00 am

GDSII and LEF min

For IC designs there are many data formats used throughout the logical and physical design process, and one of those file formats is called LEF, an acronym for Library Exchange Format, created by Tangent, an early EDA company with Place and Route tools that was acquired by Cadence way back in March 1989. LEF generation times can become… Read More


Cadence adds a new Fast SPICE Circuit Simulator

Cadence adds a new Fast SPICE Circuit Simulator
by Daniel Payne on 06-02-2021 at 10:00 am

SPICE spectrum. Fast SPICE

In the early years of Cadence their growth was bolstered through many well-timed acquisitions, however over the last several years I’ve noticed a distinctively different trend where they have internally developed EDA tools. I had a Zoom call with Jay Madiraju from Cadence, who markets their newly announced Fast SPICE … Read More


IoT’s Inconvenient Truth: IoT Security Is a Never-Ending Battle

IoT’s Inconvenient Truth: IoT Security Is a Never-Ending Battle
by Dana Neustadter on 06-01-2021 at 10:00 am

IoTs Inconvenient Truth IoT Security Is a Never Ending Battle

The continued innovation and widespread adoption of connected devices — the internet of things (IoT) — has resulted in a vast range of conveniences that improve our lives every day. At the same time, the ubiquity of IoT devices, which market watchers estimate to be in the tens of billions, also makes it more attractive to bad actors… Read More


From Silicon To Systems

From Silicon To Systems
by Daniel Payne on 05-31-2021 at 10:00 am

digitalization min

The annual Siemens Digital Industries Software user group event was held virtually on May 26th, which made it easy to attend from my home office, although selecting from the list of speakers was a challenge, because they offered 475 sessions, wow. My focus is EDA, so I listened to Joseph Sawicki, the Executive Vice President, IC … Read More


Heterogeneous Chiplets Design and Integration

Heterogeneous Chiplets Design and Integration
by Kalar Rajendiran on 05-28-2021 at 6:00 am

Transistor Cost per Billion 3nm Projection

Over the recent years, the volume and velocity of discussions relating to chiplets have intensified. A major reason for this is the projected market opportunity. According to research firm Omdia, chiplets driven market is expected to be $6B by 2024 from just $645M in 2018. That’s an impressive nine-fold projected increase over… Read More


Siemens EDA Acquires an IP Validation Tool for standard cells, IO and Hard IP

Siemens EDA Acquires an IP Validation Tool for standard cells, IO and Hard IP
by Daniel Payne on 05-27-2021 at 10:00 am

fractal CrossFire min

We’re living in an era of good growth for semiconductor design companies, and it’s no secret that each new SoC that comes along contains hundreds of IP blocks, so IP design re-use is just an accepted way of getting to market more quickly with lower risks. But how do we really know that all of the new IP is really correct? … Read More