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Next generation electronic systems require an engineering approach incorporating a digital twin methodology for early verification with digital prototypes. Over the course of a design project, the digital twin model evolves to allow more complex interactions including analysis, simulations and validations earlier… Read More
Soft errors change stored data and cause temporal malfunctions in electronic systems. This mainly occurs when radiation particles collide with semiconductor devices. Soft errors are a concern in all environments, whether in the atmosphere, in space, or on the ground.
Soft errors are critical in high-reliability applications… Read More
We’re getting close to the annual July Design Automation Conference (DAC) in San Francisco, and every year I like to make the rounds of the exhibitors beforehand and see what’s new. When I checked with AMIQ EDA, I found that this is a big year for them. Their parent company AMIQ just reached its 20th anniversary, and they’ll be celebrating… Read More
I’d like to extend an invitation to you and your development team to visit with Agnisys in our booth, #2512, at this week’s Design Automation Conference (DAC) 2023, Monday, July 10-12.
In its 60th year, DAC is recognized as the premier event for the design and design automation of electronic chips to systems, so you can count on team… Read More
Aberration-free optics are bulky and expensive. Thanks to high-performance AI-enabled processors and GPUs with abundant processing capabilities, image quality nowadays relies more on high computing power tied to miniaturized optics and sensors. Computational imaging is the new trend in imaging and relies on the fusion … Read More
I recall an early custom IC designed at Wang Labs in the 1980s without any DFT logic like scan chains, then I was confronted by Prabhu Goel about the merits of DFT, and so my journey on DFT began in earnest. I learned about ATPG at Silicon Compilers and Viewlogic, then observability at CrossCheck where I met Jennifer Scher, now she’s… Read More
Constrained random methods in simulation are universally popular, still can the method be improved? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More
The relentless advancement of mobile phone technology continues to push boundaries, demanding SoCs that deliver ever-increasing performance while preserving extensive battery life. To meet these demands, the industry is progressively embracing lower technology nodes with current designs being taped-out at 5nm or below.… Read More
Keysight EDA will have a large presence at this year’s DAC in San Francisco July 9-13. For a better understanding of what’s happening with Keysight EDA at DAC I talked to my contacts to learn that they have three main messages this year:
• Automate
• Collaborate
• Innovate
Demos: Booth 1531
You may recall that Keysight acquired Cliosoft… Read More
The Risk of Not Optimizing Clock Power