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Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability
by Kalar Rajendiran on 11-27-2023 at 6:00 am

Synopsys 224G SerDes IP InterOp Multiple Tradeshows

Hyperscale data centers are evolving rapidly to meet the demands of high-bandwidth, low-latency applications, ranging from AI and high-performance computing (HPC) to telecommunications and 4K video streaming. The increasing need for faster data transfer rates has prompted a scaling of Ethernet from 51Tb/s to 100Tb/s. Numerous… Read More


Generative AI for Silicon Design – Article 4 (Hunt for Bugs)

Generative AI for Silicon Design – Article 4 (Hunt for Bugs)
by Anshul Jain on 11-23-2023 at 8:00 am

Generative AI for Silicon Design 4

In the complex world of silicon design, ensuring the accuracy and reliability of our designs is paramount. As our chips become more sophisticated, the process of bug hunting—identifying and rectifying errors in our designs—becomes even more critical. Generative AI has the potential to revolutionize the silicon design industry… Read More


Handling metastability during Clock Domain Crossing (CDC)

Handling metastability during Clock Domain Crossing (CDC)
by Daniel Payne on 11-22-2023 at 10:00 am

synchronizer min

SoC designs frequently have lots of different clock domains to help manage power more efficiently, however one side effect is that when the clock domains meet, i.e., in a Clock Domain Crossing (CDC), there’s the possibility of setup and hold time violations that can cause a flip-flop to become metastable. Synchronizer … Read More


Cadence Integrates Power Integrity Analysis and Fix into Design

Cadence Integrates Power Integrity Analysis and Fix into Design
by Bernard Murphy on 11-21-2023 at 6:00 am

Voltus Insight AI min

As integration levels increase, clock frequencies rise, and feature sizes shrink it is not surprising that all or most aspects of semiconductor design become more complex and demand more from design technologies. One example where the traditional approach is breaking down is in optimizing power distribution networks (PDNs)… Read More


Accelerating Development for Audio and Vision AI Pipelines

Accelerating Development for Audio and Vision AI Pipelines
by Bernard Murphy on 11-15-2023 at 6:00 am

AI pipeline min

I wrote previously that the debate over which CPU rules the world (Arm versus RISC-V) somewhat misses the forest for the trees in modern systems. This is nowhere more obvious that in intelligent audio and vision: smart doorbells, speakers, voice activated remotes, intelligent earbuds, automotive collision avoidance, self-parking,… Read More


Generative AI for Silicon Design – Article 3 (Simulate My Design)

Generative AI for Silicon Design – Article 3 (Simulate My Design)
by Anshul Jain on 11-14-2023 at 10:00 am

Generative AI for Silicon Design

Generative AI has time and again showcased its power to understand, predict, and explain a myriad of phenomena. Beyond its famed applications in art and text, it’s making ripples in the niche realm of hardware engineering. In this article, our exploration focuses on the potential of Generative AI to comprehend and predict… Read More


Uniquely Understanding Challenges of Chip Design and Verification

Uniquely Understanding Challenges of Chip Design and Verification
by Daniel Nenni on 11-14-2023 at 6:00 am

Jean Marie Brunet (1)

Jean-Marie Brunet is Vice President and General Manager of Siemens Hardware-Assisted Verification. He and I spoke recently about how different his hardware group is from the rest of the software-centric EDA product space and why a hardware-oriented EDA vendor like Siemens fully understands the challenges of the chip design… Read More


New STA Features from Cadence

New STA Features from Cadence
by Daniel Payne on 11-13-2023 at 10:00 am

Tempus DRA Suite

Static Timing Analysis (STA) has been an EDA tool category for many years now, yet with each new generation of smaller foundry process nodes come new physical effects that impact timing, requiring new analysis features to be added. For advanced process nodes, there are five different types of analysis that must be included when… Read More


Successful 3DIC design requires an integrated approach

Successful 3DIC design requires an integrated approach
by Kalar Rajendiran on 11-13-2023 at 6:00 am

Siemens EDA 3DIC Graphics

While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal… Read More


IROC at the TSMC Open Innovation Ecosystem Platform

IROC at the TSMC Open Innovation Ecosystem Platform
by Daniel Nenni on 11-09-2023 at 6:00 am

TSMC OIP IROC

Radiation is everywhere. Radiation contributes to Single Event Effects (SEE) in semiconductor circuits and packaging. As chips get larger, containing more functions, and using lower voltage to reduce power, SEEs have become more significant to product reliability, Failures In Time rates (FIT), and meantime between failures… Read More