This year is proving to be a momentous one for U.S. semiconductor manufacturing. During a global chip shortage and record inflation, President Biden signed into effect the CHIPS and Science Act – which so far is the greatest boon to U.S. semiconductor manufacturing in history, with $52 billion in subsidies for chip manufacturers… Read More
Electronic Design Automation
Measuring Success in Semiconductor Design Optimization: What Metrics Matter?
When it comes to electronic design automation (EDA), there are two aspects to this technologically challenging and highly competitive field. First, there is the task of designing very complex chips for which a full suite of various software tools are needed. Then there is the task of managing extremely complex EDA workflows and… Read More
The Increasing Gaps in PLM Systems with Handling Electronics
Product LifeCycle Management (PLM) systems have shown incredible value for integrating the enterprise with a single view of the product design, deployment, maintenance, and end-of-life processes. PLM systems have traditionally grown from the mechanical design space, and this still forms their strength.
Meanwhile, due… Read More
DFT Moves up to 2.5D and 3D IC
The annual ITC event was held the last week of September, and I kept reading all of the news highlights from the EDA vendors, as the time spent on the tester can be a major cost and the value to catching defective chips from reaching production is so critical. Chiplets, 2.5D and 3D IC design have caught the attention of the test world, … Read More
Siemens EDA Discuss Permanent and Transient Faults
This is a topic worth coverage for those of us who aim to know more about safety. There are devils in the details on how ISO 26262 quantifies fault metrics, where I consider my understanding probably similar to other non-experts: light. All in all, a nice summary of the topic.
Permanent and transient faults 101
The authors kick off … Read More
Analyzing Clocks at 7nm and Smaller Nodes
In the good old days the clock signal looked like a square wave , and had a voltage swing of 5 volts, however with 7nm technology the clock signals can now look more like a sawtooth signal and may not actually reach the full Vdd value of 0.65V inside the core of a chip. I’ll cover some of the semiconductor market trends, and then challenges… Read More
Webinar: Post-layout Circuit Sizing Optimization
My IC design career started out with manually sizing transistors to improve performance, while minimizing layout area and power consumption. Fortunately we don’t have to do manual transistor sizing anymore, thanks to EDA tools that are quicker and more accurate than manual methods. MunEDA is an EDA vendor that has developed… Read More
New ECO Product – Synopsys PrimeClosure
New EDA product launches are always an exciting time, and I could hear the energy and optimism from the voice of Manoj Chacko at Synopsys in our Zoom call about Synopsys PrimeClosure. During the physical implementation phase for IC designs there’s a big challenge to reach timing closure, and with advanced nodes the number… Read More
Test Ordering for Agile. Innovation in Verification
Can we order regression tests for continuous integration (CI) flows, minimizing time between code commits and feedback on failures? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas.… Read More
Whatever Happened to the Big 5G Airport Controversy? Plus A Look To The Future
In December 2021, just weeks before Verizon and AT&T were set to enable their new radio access networks in the 5G mid-band spectrum (also known as C-Band), the Federal Aviation Administration (FAA) released a Special Airworthiness Information Bulletin (SAIB) and a statement notifying operators of potential 5G interference… Read More
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