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Electronic Design Automation
Introduction of 2.5D and 3D multi-die based products are helping extend the boundaries of Moore’s Law, overcoming limitations in speed and capacity for high-end computational tasks. In spite of its critical function within the 3DIC paradigm, the interposer die’s role and related challenges are often neither fully comprehended… Read More
Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.… Read More
As SoC complexities continue to expand to billions of transistors, the quest for higher levels of design automation also rises. This has led to the adoption of High-Level Synthesis (HLS), using design languages such as C++ and SystemC, which is more productive than traditional RTL design entry methods. In the RTL approach there… Read More
I recently had an eye-opening discussion regarding the phenomena of soft errors in semiconductor devices. I always knew this could be a problem in space, where there are all kinds of high energy particles. What I didn’t realize is there are two trends that are making this kind of problem relevant on the ground as well as in space. The… Read More
In the fast-paced world of Electronic Design Automation (EDA), the complexity of chip designs is continuously rising. With the burgeoning of systems such as 5G communication devices and Advanced Driver-Assistance Systems (ADAS) teeming with thousands of components, the demand for robust and efficient prototyping platforms… Read More
Dieter Therssen obtained his master’s degree in Electronics Engineering from KU Leuven in 1987. He started his career as a hardware design engineer, using IMEC’s visionary tools and design methodologies in the early days of silicon integration.
Since then, Dieter developed his career across many digital technologies,… Read More
At the recent User2user conference, Amit Kumar, Principal Hardware Engineer, Microsoft, shared the company’s experience from building a 3DIC SoC and highlighted Siemens EDA tools that were used. The following is a synthesis of core aspects of that talk.
Despite the numerous advantages of 3DIC technology, its… Read More
Today’s advanced node chip designs are faced with many new complexities from design and verification down to manufacturing. The solutions used at every stage of chip development generate petabytes of data. Managing, analyzing, understanding, and acting upon that data is overwhelming and paralyzing. Manual interpretation… Read More
PCB designers have been using manual routing for decades now, so when is it time to consider adding interactive routing technologies to become more productive? Manually routing traces to connect components will take time from a skilled team member and involves human judgement that will introduce errors. When a design change … Read More
Synopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a recent in-depth article on the make-up of the ARC-V family on SemiWiki here. This is important and impactful news; I encourage you to read these articles if you haven’t… Read More
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Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability