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EDA

Electronic Design Automation

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Multi-Mode Simulation – What’s New at Cadence?

Multi-Mode Simulation – What’s New at Cadence?
by Daniel Payne on 11-21-2011 at 6:52 pm
Categories: Cadence, EDA

Every week I receive several webinar invitations, so the recent one from Cadence about Virtuoso Multi-Mode simulation caught my fancy because I had met with John Pierce at DAC and wanted to see what was new since then and see how they compared with Mentor and Synopsys tools.


John Pierce, Product Marketing Director

This webinar runs… Read More

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The Power of the Platform!

The Power of the Platform!
by Daniel Nenni on 11-16-2011 at 10:06 am
Categories: Cliosoft, EDA

The Nintendo Wii is one of the most successful gaming platforms with the most diverse set of games — from fun games that can be enjoyed by the whole family to fitness programs that can be used by adults. They beat the dominant Sony Playstation and the Microsoft Xbox by thinking outside the box and creating a platform that was really… Read More

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Formally verifying protocols

Formally verifying protocols
by Paul McLellan on 11-15-2011 at 1:19 pm
Categories: EDA

I attended much of the Jasper users’ group a week ago. There were several interesting presentations that I can’t just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper’s products on a daily basis.

But for me the most interesting presentations were several… Read More

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Physical Verification of 3D-IC Designs using TSVs

Physical Verification of 3D-IC Designs using TSVs
by Daniel Payne on 11-12-2011 at 10:36 am
Categories: EDA, Foundries, Siemens EDA, TSMC

3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were… Read More

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EDA Interoperability Forum

EDA Interoperability Forum
by Paul McLellan on 11-09-2011 at 3:06 pm
Categories: EDA, Synopsys

The 24th Interoperability Forum is coming up at the end of the month on November 30th to be held at the Synopsys compus in Mountain View. It lasts from 9am until lunch (and yes, Virginia, there is such a thing as a free lunch). I think it looks like a very interesting way to spend a morning.

Here are the speakers and what they are speaking… Read More

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Synopsys Awarded TSMC’s Interface IP Partner of the Year

Synopsys Awarded TSMC’s Interface IP Partner of the Year
by Eric Esteve on 11-09-2011 at 9:19 am
Categories: Foundries, IP, Synopsys, TSMC

Is it surprising to see that Synopsys has been selected Interface IP partner of the year by TSMC? Not really, as the company is the clear leader on this IP market segment (which includes USB, PCI Express, SATA, DDRn, HDMI, MIPI and others protocols like Ethernet, DisplayPort, Hyper Transport, Infiniband, Serial RapidIO…). But,… Read More

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RTL Power Models

RTL Power Models
by Paul McLellan on 11-08-2011 at 8:00 am
Categories: Ansys, Inc., EDA

One of the challenges of doing a design in the 28nm world is that everything depends on everything else. But some decisions need to be made early with imperfect information. But the better the information we have, the better those early decisions will be. One area of particular importance is selecting a package, designing a power… Read More

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Managing Test Power for ICs

Managing Test Power for ICs
by Beth Martin on 11-07-2011 at 12:17 pm
Categories: EDA, Siemens EDA

The goal for automatic test pattern generation (ATPG) is to achieve maximum coverage with the fewest test patterns. This conflicts with the goals of managing power because during test, the IC is often operated beyond its normal functional modes to get the highest quality test results. When switching activity exceeds a device’s… Read More

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Learning Verilog for ASIC and FPGA Design

Learning Verilog for ASIC and FPGA Design
by Daniel Payne on 11-02-2011 at 11:17 am
Categories: EDA

Verilog History
Prabhu Goel founded Gateway Design Automation and Phil Moorby wrote the Verilog language back in 1984. In 1989 Cadence acquired Gateway and Verilog grew into a de-facto HDL standard. I first met Prabu at Wang Labs in 1982 where I designed a rather untestable custom chip named the WL-2001 (yes, it was named to honor… Read More

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High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!
by Daniel Nenni on 11-01-2011 at 9:00 am
Categories: EDA, Foundries, Solido, TSMC

Hello Daniel,
I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER… Read More