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Electronic Design Automation
Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More
At DesignCon this week there was a panel on 3D standards organized by Si2. I also talked to Aveek Sarkar of Apache (a subsidiary of Ansys) who is one of the founding member companies of the Si2 Open3D Technical Advisory Board (TAB), along with Atrenta, Cadence, Fraunhofer Institute, Global Foundries, Intel, Invarian, Mentor, Qualcomm,… Read More
Always in motion is the future. ~Yoda
For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More
Next week there are two Apache, a subsidiary of Ansys, events. At DesignCon there are a couple of workshops on chip-package-system (CPS). In addition to Apache themselves, each of the two workshops has a number of representatives of leading edge companies doing semiconductor design. I already blogged about this in more detail… Read More
For the greater good of the semiconductor ecosystem, SemiWiki and Mentor Graphics present SemiWiki Seminars, a free seminar and software demonstration series addressing the latest innovations in IC design. SemiWiki Seminars discuss interesting new challenges and potential solutions aimed at increased circuit density … Read More
For the greater good of the semiconductor ecosystem, I have agreed to Co-Chair the 2012 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), the “Premier International Gathering for Commercial and Academic Reconfigurable Computing Application Developers”, July 16-19, 2012,… Read More
Most IC designers I talk to really enjoy the creative process of developing a new SoC design, debugging it, then watching it go into production. They don’t really like spending time learning how to make their EDA tools work together in an optimal IC design flow where they may have a dozen tools each with dozens of options. Fortunately… Read More
Looking at the huge gap between the revenue of semiconductor design and manufacturing (~$300B) and that of EDA tools, services and silicon IP combined (~6B) inspired me to look more deeply into the overall arena of semiconductors in today’s context and possibly decipher some trends which should emerge in near future. Although… Read More
Users of Cadence Virtuoso tools for IC layout and schematics can make their design flow easier by using Design Data Management tools from ClioSoft. Keeping track of versions across schematics, layout, IP libraries and PDKs can be daunting. Come and learn more about this at a Webinar hosted by ClioSoft next Tuesday.… Read More
3D and 2.5D (silicon interposer) designs create new challenges for EDA. Not all of them are in the most obvious areas. Mentor has an interesting presentation on what is required for verification and testing of these types of designs. Obviously it is somewhat Mentor-centric but in laying out the challenges it is pretty much agnostic.… Read More
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Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business