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EDA

Electronic Design Automation

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Cadence EDA360 is Paper!

Cadence EDA360 is Paper!
by Daniel Nenni on 05-08-2011 at 4:02 pm
Categories: Cadence, EDA

Hard to believe a year has gone by since the big announcement of the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat! Having spent more time on it that I should have, here is my opinion on EDA360 on its first anniversary.

Richard Georing did a very nice anniversary piece “Ten Key… Read More

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Chip Power Models

Chip Power Models
by Paul McLellan on 05-04-2011 at 4:21 pm
Categories: Ansys, Inc., EDA

As the complexity of the chip-package-system (CPS) interactions has increased, the tradeoffs in doing a power and noise analysis has had to gradually increase. As is so often the case in semiconductor designs, issues first arise as second-order effects that can largely be ignored but each process node makes the problem worse … Read More

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Apache at DAC

Apache at DAC
by Paul McLellan on 05-04-2011 at 2:38 pm
Categories: Ansys, Inc., EDA

DAC is less than a month away, June 6-8th for the tradeshow, longer depending on what other events you might also be attending. Apache is in booth 2448 (marked in red on the DAC floorplan map.

Many of the presentations at the Apache booth will be customers (such as ARM, Xilinx, ST Ericsson, GlobalFoundries and TSMC) discussing various… Read More

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Two New Platforms for Systems Designers

Two New Platforms for Systems Designers
by Daniel Payne on 05-03-2011 at 7:03 pm
Categories: Cadence, EDA

Introduction
Today Cadence announced at the Embedded Systems Conference something of interest to systems designers.

What’s New?
The Rapid Prototyping Platform and Virtual System Platform are what’s new, and they intend to enable and automate concurrent hardware and software development. I can remember Mentor… Read More

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Graphical DRC vs Text-based DRC

Graphical DRC vs Text-based DRC
by Daniel Payne on 05-01-2011 at 11:42 am
Categories: EDA, Siemens EDA

Introduction
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.

At the 28nm node a typical DRC (Design Rule Check) deck will… Read More

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Mentor 2 : Carl Icahn 0

Mentor 2 : Carl Icahn 0
by Daniel Nenni on 05-01-2011 at 9:46 am
Categories: EDA

The corporate raiders are still throwing rocks at Mentor Graphics. I have followed this reality show VERY closely and find their latest assault seriously counterproductive. Disinformation is common in EDA but I expected more from Carl Icahn and the Raiderettes. They are quite the drama queens. Here is a billion dollar question:… Read More

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Ivo Bolsens of Xilinx and Crossover Designs

Ivo Bolsens of Xilinx and Crossover Designs
by Paul McLellan on 04-27-2011 at 4:14 pm
Categories: EDA, Siemens EDA

I was at Mentor’s u2u (user group) meeting and one of the keynotes was by Ivo Bolsens of Xilinx. The other was by Wally Rhines and is summarized here.

Ivo started off talking analogizing SoCs as the sports-cars of the industry (fast but expensive), and FPGAs as the station wagons (not cool). In fact he even said that when Xilinx… Read More

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Wally’s u2u keynote

Wally’s u2u keynote
by Paul McLellan on 04-27-2011 at 3:25 pm
Categories: EDA, Siemens EDA

I was at Wally’s u2u (Mentor user group) keynote yesterday. The other keynote was by Ivo Bolsens of Xilinx and is here. He started off by looking at how the semiconductor industry has recovered and silicon area shipments are now back on trend after a pronounced drop in 2009 and revenue has followed. Finally the semiconductor… Read More

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Semiconductor RTL Power Analysis: the sweet spot

Semiconductor RTL Power Analysis: the sweet spot
by Paul McLellan on 04-26-2011 at 4:20 pm
Categories: Ansys, Inc., EDA

Power has become the strongest driver of semiconductor design today, more important than area, more important than timing. Whether the device is handheld, like a wireless phone, or tethered, like a router, complex power and energy requirements must be met. Shrinking geometries continue to impose new challenges as power management… Read More

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How Avnera uses Hardware Configuration Management with Virtuoso IC Tools

How Avnera uses Hardware Configuration Management with Virtuoso IC Tools
by Daniel Payne on 04-21-2011 at 12:12 pm
Categories: Cadence, Cliosoft, EDA

Introduction
Here in the Silicon Forest (Oregon) we have a venture-backed, fabless analog semi company called Avnera that has designed over 10 Analog System on Chips (ASoC). Their chips are used in consumer products for both wireless audio and video applications.

 

James Rollins is the director of physical design at Avnera… Read More