In June I’ll be visiting several first time companies at DAC in order to learn more about what they have to offer in terms of EDA software, then blog about what I discover.
Here’s my list:
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| EDA Software, IP or Service
| DXCorr is a privately held silicon valley company focused on providing best-in-class embedded solutions- foundation IP- CAMs, memory compilers, standard cells, RTL2GDS2 full-service flow, custom EDA and design automation/ CAD services, PCELLs and PDK’s. DXCorr specializes in power-, performance- and area-optimized IP development, plus high-end chip development services. DXCorr products and services have met the demanding needs of a competitive customer base which includes Tier 1 foundries, IP providers, fabless semiconductor companies and IDMs looking for differentiation. and time to market advantages.
| Huada Empryan Software
| Huada Empyrean Software Co., Ltd. ( HES) is China’s largest EDA company. Headquartered in Beijing, with ~300 employees worldwide, HES provides a complete analog/mixed signal design platform and SOC back-end timing closure tools.
| ICScape (Santa Clara, CA) develops and markets next generation design closure solutions for SOC designs and an integrated suite of Analog/Mixed Signal design tools for applications including, storage, wireless, data communication, multimedia, image sensor and power management.
ICScape recently became a subsidiary of Huada Empyrean Software (HES – see separate listing), China’s largest EDA company. HES is funded by CEC (China Electronic Corporation), the largest electronics company in China.
| Integrand Software
| Integrand Software’s full-wave 3D EM simulation tool EMX®, allows designers to accurately and efficiently simulate large RF circuit blocks, characterize the behavior of passive components and analyze the parasitics due to interconnect. EMX is very fast (seconds for an inductor), very accurate (within a few percent of measurements) and easy to use (seamlessly integrated in Cadence). EMX is widely used for designing inductors, baluns, VCOs, LNAs, packages, bondwires and interconnect and can also generate passive RLCK Spice models from layout.
| Invarian’s EDA tool suite Pioneer contains a comprehensive sign-off analysis solution (InVar) to ensure first time tape-out success. To effectively model events in the real-world today’s designers must account for various transient effects. Complex algorithms to model this behavior with accurate, complete and fast results is at the heart of Invarian’s tool suite Pioneer. Invarian’s sign-off analysis for analog, digital and mixed signal integrated circuits identifies post-manufacturing failures before expensive tape-outs. Incorporating many what-if tools to assist designers to navigate around potential perils without interrupting the overall flow in either extended time in simulation or added engineering resources is key to achieving the overall goal of maintaining our customers time-to-market objectives with added insurance of first-time success. Pioneer reports real life behavior of integrated circuits as it takes packaging into account, and simulates integrated circuits in a continuous space of temperatures and voltages. The Pioneer suite’s ability to fully support 3D modeling enables accurate simulation across multiple boundaries, such as interposers, heat-sinks, solder bumps, stacked die and their associated interconnects. Our tool performs concurrent analysis for power, temperature, timing, and effective voltage and eliminates traditional error-prone over-constraining.
| Jedat provides the automation of custom layout design with design constraint check and electromigration analysis in the early design stage. With more than 4000 licenses installed worldwide, Jedat’s proven technologies have reduced TAT by over 80% compared to conventional design techniques and costly iterations of circuit and layout design.
Some Alpha-SX tools include:
1. High performance Analog MOS layout & analyze tools of the Anchor suite
2. Ultra high performance Spice waveform viewer
3. Hotspot check for terabytes of various layout data formats
| Symica is an Electronic Design Automation (EDA) company developing tools for the analog and mixed-signal integrated circuit design. Symica provides a suite of EDA tools for schematic entry, SPICE simulation, mixed-signal simulation, simulation result analyzing and layout drawing. All Symica tools are integrated into and can be run from Symica Design Environment, except SymLayout, which is working as a separate application. Symica Design Environment also integrates additional modules required for circuit design: Library manager, Schematic editor, Symbol editor, Hierarchy editor, Simulation environment, input/output translators, etc.
| Synaptic & Trams
| SYNAPTICtargets the optimization of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels. Research efforts are focused on exploring and developing innovative design methodologies and EDA tools. http://www.synaptic-project.eu
TRAMStargets the design of devices models for sub-16nm, bulk-CMOS, CNTFETs, FinFETs, III-V/Ge technologies including variability and aging mechanisms. It covers research on new compensating, tolerating and reconfiguration mechanisms to mitigate the variability effects at circuit and many-core system level. http://trams-project.upc.edu
Don’t worry if you’re company name isn’t listed above, I will be visiting many other EDA companies as well (Cadence, Synopsys/Magma, Mentor, Tanner EDA, ClioSoft, etc.) to get an update on transistor-level tools.
For EDA historians you can read all of my 2011 DAC trip reports here:
- Sunday Night at DAC
- Magma, ARM, Globalfoundries
- Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop
- FineSim adds RF analysis and Tcl Circuit Checks
- IPL Alliance focuses on iPDKs and Analog Constraints
- Physical IP group at ARM
- Tanner EDA at DAC
- Extreme DA at DAC
- Synopsys IC Validator
- Circuit Simulation and IC Layout update from Mentor
- DRC tool guns for Calibre at DAC
- An Affordable 3D Field Solver
- Hardware Configuration Management at DAC
- Circuit Simulation Update from Cadence at DAC
- Reduced IC Leakage at DAC
- Cadence Spinout at DAC
- RLCK Reduction Tool at DAC
- Ciranova Update at DAC
- EDA Interoperability at DAC
- One Trillion Transistor IC Layout at DAC
- Berkeley Design Automation at DAC
- Blue Pearl at DAC
- Synopsys, ARM, Samsung, Globalfoundries (Part 1)
- Synopsys, ARM, Samsung, Globalfoundries (Part 2)
- CyberEDA Adds a Transistor-level Debugger
- QuickCap for IC Extraction at DAC
- HSPICE gets Faster, better Convergence
- Invarian and AnaGlobe