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Electronic Design Automation
I decided to attend a webinar today hosted by Synopsys, “Streamline Your PrimeTime ECO Flow For Fastest Setup, Hold and Timing DRC Closure.” The format was to present slides first then hold for questions until the end. Enough time was spent on questions which made this webinar different than most other webinars I’ve… Read More
There were three keynotes at CDNLive this morning, and one theme ran through them: collaboration. In fact there was one specific instance of collaboration that all three people mentioned. Taping out an ARM Cortex-A15 in TSMC 20nm technology using a Cadence tool flow.
Lip-Bu, Cadence’s CEO, went first. He had some numbers… Read More
I love to read good news about growth in EDA especially when our industry has seen single-digit growth for several years now. What I read on March 8th from ClioSoft stated a 53% increase in bookings for 2011, now that’s what I call growth.
ClioSoft provides Hardware Configuration Management (HCM) software to EDA users typically… Read More
Designing larger than ever SoC, integrating multiple ARM’s Cortex-A15 and Cortex-A9 microprocessor cores as well as complexes IP functions like HDMI controller, DDR3 Memory controller, Ethernet, SATA or PCI Express controller are pushing designers to search for better price, performance and area tradeoffs and the SoC interconnect… Read More
As this blog is being posted I’m on my way to Dresden for the 2012 Design Automation and Test Conference. DATE used to bounce between Munich and Paris, I have attended many times but not in the past couple of years. No excuse really, just busy with other things. DATE 2012 Highlights in Dresden include E-Mobility and More-than-Moore… Read More
Last month Brian Bailey at EDN moderated an interesting webinar about power issues. Unusually, it combined two different domains: doing things by modeling and actually taking measurements off real chips and boards. The two participants were Arvind Shanmugavel from the Apache subsidiary of Ansys, and Randy White from Tektronix.… Read More
Next Wednesday is the Common Platform Technology Forum. “Common Platform” is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and… Read More
With DATE next week in Dresden, all eyes turn to Germany. Not to be left out, Jasper has a seminar on formal verification coming up on March 19th in the Kempinski Hotel at Munich airport. Unlike most “airport” hotels the Kempinski is indeed right in the heart of the airport. And for those of us who like a good German beer,… Read More
Next Tuesday and Wednesday, March 13-14th, is CDNLive in Silicon Valley at the DoubleTree Hotel (which I see we are now meant to call DoubleTree by Hilton, although I still have to think twice not to call it the Red Lion, the group whose CFO at one point was Ray Bingham who was CFO and then CEO of Cadence. Trivia fact for the day).
CDNlive… Read More
There is an interview in the San Jose Mercury News with Kathryn Kranen, Jasper’s CEO. Of course the Mercury is a general newspaper and can’t expect most of its readership to have a clue what EDA is, never mind formal verification. It’s a similar problem to the one we all have when we try and explain to our families… Read More
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Intel’s Pearl Harbor Moment