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Electronic Design Automation
It is well-known that semiconductor growth is driven by AI. That simple statement breaks down into many complex use cases, each with its own requirements and challenges. A webinar will be presented by Synopsys on October 23 that focuses on the specific requirements for one of the most popular use cases – AI at the edge. The speaker… Read More
Why should high frequency circuit designers consider stability early in the design process? Isn’t there enough to worry about just making the circuit function at the fundamental frequency?
In the past, Microwave Engineers used to solve stability problems in the lab, perhaps adding bypassing or loss in a strategic location to… Read More
![[white paper] Parasitic Analysis Figures](https://semiwiki.com/wp-content/uploads/2025/10/Fig1-net-level-visualization-150x127.jpg)
By Omar Elabd
As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More
Many years ago, not long after we first launched SpyGlass, I was looking around for new areas where we could apply static verification methods and was fortunate to meet Ralph Marlett, a guy (now friend) with extensive experience in DFT. Ralph joined us and went on to build the very capable SpyGlass DFT app. So capable that SpyGlass… Read More
Over the years design reuse methodology created a market for Semiconductor IP (SIP), now with formal techniques there’s a need for Assertion IP (AIP). Where each AIP is a reusable and configurable verification component used in hardware design to detect protocol and functional violations in a Design Under Test (DUT). LUBIS … Read More
Synopsys recently held a webinar session on this topic and Gustavo Pimentel, Principal Product Marketing Manager at the company led the webinar session. Going into the webinar session, I found myself wondering: why focus on PCIe 5.0, eight years after its release? With the industry buzzing about Edge AI, cloud computing, and … Read More
By Mark Tawfik
Overview: Protecting ICs from costly ESD and latch-up failures
Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].
Ensuring the robust protection of integrated circuits (ICs) against various… Read More
Daniel is joined by Dr. Mark Burton, the General Chair for this year’s DVCon Europe. DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits.
Mark shares his long history of involvement in DVCon with Dan. He … Read More
Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC… Read More
For decades, chip design has been a delicate balance of creativity and drudgery. Architects craft detailed specifications, engineers read those documents line by line, and teams write and debug thousands of lines of Verilog and UVM code. Verification alone can consume up to 35 percent of a project’s cost and add many months to … Read More
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AI RTL Generation versus AI RTL Verification