Keysight, with deep roots tracing back to Hewlett-Packard, has long been at the forefront of innovation in electronic design and testing. It manufactures electronics test and measurement equipment and software. The company also owns its own foundry and makes custom chips and packages for its instrumentation business. Many… Read More
Electronic Design Automation
Getting Faster DRC Results with a New Approach
As IC designs become increasingly complex, traditional Design Rule Checking (DRC) methods are struggling to keep up. The old “construct by correction” approach, initially developed for simpler, custom layouts, is creating substantial runtime and resource bottlenecks. Traditional DRC relies on an iterative, sequential… Read More
What is Different About Synopsys’ Comprehensive, Scalable Solution for Fast Heterogeneous Integration
Multi-die design has become the center of a lot of conversation lately. The ability to integrate multiple heterogeneous devices into a single package has changed the semiconductor landscape, permanently. This technology has opened a path for continued Moore’s Law scaling at the system level. What comes next will truly be exciting.… Read More
2025 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
Tell us a little bit about yourself and your company, AMIQ EDA.
We are an EDA company providing software tools targeting both chip design and chip verification. Our tools enable engineers to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology… Read More
Automating Formal Verification
Formal verification methods are being adopted at a fast pace as a complement to traditional verification methods like functional simulation for IP blocks in SoC designs. I had a video meeting with Max Birtel, co-founder of LUBIS EDA and learned more about their history, products and vision. This company started recently in 2020… Read More
2024 Retrospective. Innovation in Verification
As usual in January we start with a look back at the papers we reviewed last year. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.
The 2024 Picks
These … Read More
Full Spectrum Transient Noise: A must have sign-off analysis for silicon success
Noise minimization is required for advanced analog and radiofrequency (RF) circuits. Unlike digital circuits, where noise is a second-order effect, system performance metrics such as signal-to-noise ratio (SNR), phase noise, timing jitter, and bit error rate (BER) are directly affected in analog and RF designs. Effective… Read More
PSS and UVM Work Together for System-Level Verification
In the early days of the PSS rollout, some verification engineers were suspicious. Just as they were beginning to get comfortable with UVM, here came yet another standard to add to their learning and complexity overhead. Then the fog started to clear; UVM is ideal for block-level testing whereas PSS is ideal for system level testing.… Read More
Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More
Heterogeneous 2D/3D Packaging Challenges
A growing trend in system design is the use of multiple ICs mounted in advanced packages, especially in high-performance computing and AI. These modern packages now integrate multiple ICs, often with high-bandwidth memory (HBM), resulting in hundreds of thousands of connections that need proper verification. Traditional… Read More
Alphawave Semi is in Play!