Synopsys has been acquiring EDA and IP companies at a fast clip over the past few years and it’s often made me wonder how they are going to craft a coherent tool flow for custom IC design. At DACthis year I learned that for schematic capture the winning tool is Custom Designer SE– a relatively new tool, while the IC layout… Read More
Electronic Design Automation
Is Your Synchronizer Doing its Job (Part 2)?
In Part 1 of this topic I discussed what it takes to estimate the mean time between failures (MTBF) of a single stage synchronizer. Because supply voltages are decreasing and transistor thresholds have been pushed up to minimize leakage, the shortened MTBF of many synchronizer circuits at nanoscale process nodes is presenting… Read More
Pat Pistilli: the first cell library, the first computer-printed label and more
At the DAC 50th anniversary banquet, Pat Pistilli won the award for most tenacious attendee, having been to all 50 DACs. Well, and for creating DAC and sustaining it. He was general chair for the first DAC (not yet called DAC) and, of course, would eventually form MP Associates with his wife Marie, which still runs DAC today. In 2010… Read More
Can we really find a way to speed-up Processor & DSP core designs?
Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When… Read More
Agilent ADS Users, Find Out About Design Data Management
In May, ClioSoft and Agilent announced that Agilent’s Advanced Design System (ADS) was now integrated with ClioSoft’s SOS Design Data Management. I interviewed Greg Peterschmidt of Agilent at that time. The information page for the combined product, known as SOS viaADS is here.
Next week ClioSoft is presenting… Read More
DAC by the Numbers
The attendance numbers for DAC are out. Unless you have been living under a stone you know that DAC was in Austin Texas a couple of weeks ago. Attendance was:
- full conference passes: 1589
- exhibits-only passes: 2364
- booth staff: 1998
The registration is slightly lower than last year when DAC was in San Francisco (as it will be again … Read More
Static Low-Power Verification in Mixed-Signal SoC Designs
IC designer Shubhyant Chaturvediof AMD used EDA tools from Mentor Graphicsand Concept Engineeringto perform static, low-power verification of a mixed-signal SoC design with a combined CPU and GPU. Shubhyant presented a poster session at DAC two weeks ago in Austin, and I wanted to share it with my readers here at SemiWiki.… Read More
IC Variability Analysis at DAC
There were a handful of EDA vendors at DAC this year touting tools for IC variability analysis. On Tuesday I met with Firas Mohamed, CEO and President of Infiniscale.… Read More
A New STA Tool at DAC, No Not Cadence
The big EDA companies get big attention at DAC, however sometimes the little EDA start-ups like Arcadia Innovationhave a new product that can be overlooked. On Tuesday at DAC I met with Joey Lin, founder of Arcadia Innovation and learned about his new STA (Static Timing Analysis) tool called TimeHawk .… Read More
Deploying 14nm FinFETs in your Next Mobile SoC
At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.
Panelists included:
- Ed Sperling, Semi Mfg and Design
- Anil Jain, Cavium
- Subramani Kengeri, GLOBALFOUNDRIES
- Kelvin Low, GLOBALFOUNDRIES
- Raymond Leung, Synopsys
- Bari Biswas, Synopsys


Musk’s Orbital Compute Vision: TERAFAB and the End of the Terrestrial Data Center