CAST Compression IP Webinar 800x100 (2)
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EDA

Electronic Design Automation

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Aldec Delivers Leading Verification Methodologies!

Aldec Delivers Leading Verification Methodologies!
by Daniel Nenni on 02-14-2013 at 8:15 pm
Categories: Aldec, EDA

For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification… Read More

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Developing ARM v8 Code…Today

Developing ARM v8 Code…Today
by Paul McLellan on 02-13-2013 at 12:50 pm
Categories: Arm, EDA, IP, Synopsys

You are going to be developing software for an SoC that contains an ARM Cortex-A57 64-bit CPU. Or perhaps it is an SoC containing ARM’s hybrid big.LITTLE multi-core architecture that combines one or more low power cores with some high power, high performance cores to get the best of both worlds: high throughput when it is needed… Read More

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SoC Implementation, Sometimes You Need a Plan B

SoC Implementation, Sometimes You Need a Plan B
by Daniel Payne on 02-13-2013 at 11:14 am
Categories: EDA

I read two blogs this week that got me to thinking about contingencies in SoC implementation. By contingency I mean using an EDA tool flow from the leading vendor for logic synthesis and then discovering that you cannot route the design without expanding the die size after a few weeks of concerted effort, then having to come up with… Read More

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An Affordable AMS Tool Flow gets Integrated

An Affordable AMS Tool Flow gets Integrated
by Daniel Payne on 02-13-2013 at 11:10 am
Categories: EDA, Synopsys

EDA tools come in all sizes and price ranges, so I was pleased to readthat Tanner EDAhas completed an integration with Incentia. A few months ago Tanner announced their integration with Aldec for digital simulation, and today’s announcement extends their tool suite to include digital synthesis and static timing. Here’s… Read More

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Assertion Synthesis: Atrenta, Cadence and AMD Tell All

Assertion Synthesis: Atrenta, Cadence and AMD Tell All
by Paul McLellan on 02-11-2013 at 6:22 pm
Categories: Cadence, EDA

Assertion Synthesis is a new tool for verification and design engineers that can be used with simulation or emulation. At DVCon Yuan Lu of Atrenta is presenting a tutorial on Atrenta’s BugScope along with John Henri Jr of Cadence explaining how it helps emulation and Baosheng Wang of AMD discussing their experiences of the… Read More

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Magic? No! It’s Computational Lithography

Magic? No! It’s Computational Lithography
by Beth Martin on 02-11-2013 at 7:00 am
Categories: EDA, Siemens EDA

The industry plans to use 193nm light at the 20nm, 14nm, and 10nm nodes. Amazing, no? There is no magic wand; scientists have been hard at work developing computational lithography techniques that can pull one more rabbit out of the optical lithography hat.

Tortured metaphors aside, the goal for the post-tapeout flow is the same… Read More

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Cadence Sigrity, Together At Last

Cadence Sigrity, Together At Last
by Paul McLellan on 02-10-2013 at 9:00 pm
Categories: Cadence, EDA

In July Cadence acquired Sigrity, one of the leaders in PCB and IC packaging analysis. Until a decade ago, signal integrity and power analysis was something that only IC designers needed to worry about. For all except the highest performance boards, relatively simple tools were sufficient. Provided you hooked up the pins on all… Read More

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Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!

Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!
by Eric Esteve on 02-09-2013 at 6:18 am
Categories: Cadence, IP

If you have missed the announcement that Cosmic Circuits has been acquired by Cadence, dated February 7, you may want to read this PR. In any case, by reading this article you will understand why this acquisition is ringing the start of the “IP battle” between cadence and Synopsys. Let me remind you that I said in Semiwiki last September… Read More

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Another Winner at DesignCon

Another Winner at DesignCon
by Daniel Payne on 02-08-2013 at 5:44 pm
Categories: Ansys, Inc., EDA

After a show like DesignConwraps up we get a chance to ask ourself what it all meant, and how was this year different than last year. Reading through many posts about DesignCon I came to discover that the Awards at DesignCon are less contentious than at CES, and also that ANSYSreceived a DesignVision awardfor the 2nd year running. … Read More

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Notes from Common Platform: Collaborate or Die

Notes from Common Platform: Collaborate or Die
by Beth Martin on 02-07-2013 at 2:16 pm
Categories: EDA, Foundries, GlobalFoundries, Siemens EDA

FinFETs are hot, carbon nanotubes are cool, and collaboration is the key to continued semiconductor scaling. These were the main messages at the 2013 Common Platform Technology Forum in Santa Clara.

The collaboration message ran through most presenations, like the afternoon talk by Subi Kengeri of GLOBALFOUNDRIES and Joe Sawicki… Read More