Semiwiki 400x100 1 final
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EDA

Electronic Design Automation

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Learning about MEMS in Israel from: EDA companies, Foundry, University, Users

Learning about MEMS in Israel from: EDA companies, Foundry, University, Users
by Daniel Payne on 10-23-2012 at 12:24 pm
Categories: EDA, Synopsys

In April I attended and blogged about a webinar on MEMS and IC co-design hosted by two EDA companies: SoftMEMS and Tanner EDA. On October 30th you can attend a full-day event in Israel that is more comprehensive than the webinar that I attended.… Read More

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Hybrids on BeO then, 3D-IC in silicon now

Hybrids on BeO then, 3D-IC in silicon now
by Don Dingee on 10-21-2012 at 8:10 pm
Categories: Cadence, EDA

Once upon a time (since every good story begins that way), I worked on 10kg, 70 mm diameter things that leapt out of tubes and chased after airplanes and helicopters. The electronics for these things were fairly marvelous, in the days when surface mount technology was in its infancy and having reliability problems in some situations.… Read More

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TSMC OIP Forum 2012 Trip Report!

TSMC OIP Forum 2012 Trip Report!
by Daniel Nenni on 10-21-2012 at 6:00 pm
Categories: EDA, Foundries, TSMC

The second annual TSMC Open Integration Platform Ecosystem Forum was last week and let me tell you it was excellent. Great update on the TSMC process technology road maps, great for networking within the fabless semiconductor ecosystem, great for seeing what’s new in EDA and IP, and great for SemiWiki. It was time well spent for … Read More

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A Brief History of Aldec

A Brief History of Aldec
by Daniel Payne on 10-20-2012 at 5:31 pm
Categories: Aldec, EDA

Dr. Stanley Hyduke founded Aldecin 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Aldec maintains… Read More

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DAC: It’s the Last Week for Many Submissions

DAC: It’s the Last Week for Many Submissions
by Paul McLellan on 10-19-2012 at 2:36 pm
Categories: EDA, Events

The deadline is coming up at the end of next week (technically on Monday October 29th for those of you who like real brinkmanship) for several aspects of DAC (not submission of papers for the conference itself) but most of the less academic-oriented things.

Proposals for:

  • Special Sessions
  • Tutorials
  • Panel sessions (in the conference
… Read More
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Virtuoso Has Twins

Virtuoso Has Twins
by Paul McLellan on 10-18-2012 at 6:01 pm
Categories: Cadence, EDA

Cadence has apparently announced that going forward the Virtuoso environment is going to be split into two and offered as two separate code-streams, the current IC6.x and a new IC12.x. The idea is to introduce a new product with features that were specifically developed for new technologies such as double patterning aware layout… Read More

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TSMC dilemma: Cadence, Mentor or Synopsys?

TSMC dilemma: Cadence, Mentor or Synopsys?
by Eric Esteve on 10-18-2012 at 4:49 am
Categories: Cadence, EDA, Foundries, Siemens EDA, Synopsys, TSMC

Looking at the Press Release (PR) flow, it was interesting to see how TSMC has solved a communication dilemma. At first, let’s precise that #1 Silicon foundry has to work with each of the big three EDA companies. As a foundry, you don’t want to lose any customer, and then you support every major design flow. Choosing another strategy… Read More

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IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…

IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…
by Eric Esteve on 10-17-2012 at 4:47 am
Categories: Cadence, EDA, Events, Synopsys

… Mentor Graphics, Design & Reuse or Gartner. The IP-SoC conference in Grenoble has been the very first 100% dedicated to Design IP, created by Gabriele Saucier 20 years ago, when “reuse” was more a concept than a reality within the design teams, and when Design IP was far to be a sustainable business.

Pr Gabriele Saucier had the… Read More

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12m FPGA prototyping sans partitioning

12m FPGA prototyping sans partitioning
by Don Dingee on 10-16-2012 at 9:30 pm
Categories: Aldec, EDA, FPGA

FPGA-based prototyping brings SoC designers the possibility of a high-fidelity model running at near real-world speeds – at least until the RTL design gets too big, when partitioning creeps into the process and starts affecting the hoped-for results.

The average ASIC or ASSP today is on the order of 8 to 10M gates, and that includes… Read More

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Current Timing Closure Techniques Can’t Scale – Requires New Solution

Current Timing Closure Techniques Can’t Scale – Requires New Solution
by Daniel Nenni on 10-16-2012 at 8:30 pm
Categories: EDA


There’s a nice article on timing closure by Dr. Jason Xing, Vice President of Engineering at ICScape Inc. on the Chip Design website. Not familiar with ICScape? Paul McLellan called ICScape the The Biggest EDA Company You’ve Never Heard Ofand Daniel Payne did Schematic, IC Layout, Clock and Timing Closure from ICScape at… Read More