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Electronic Design Automation
How do you learn new hardware design topics? I just got trained online about property-based verification for hardware designers using a free online class at Aldec. The material was created by Jerry Kaczynski, a Research Engineer at Aldec.
At DAC 2012 we were hearing about the 20nm design ecosystem viability, however IC process technology never stands still so we have early process development going on now at the 10nm and 14nm nodes where FinFET technology is being touted. Earlier in February Vassilios Gerousis, a distinguished engineer at Cadence presented a session… Read More
By now, you will have seen several postings about all the different activities that are going on at Design and Verification Conference being held Feb. 25-28 at its usual location – the DoubleTree Hotel in San Jose, CA. Besides organizing an experts panel “Where Does Design End and Verification Begin?“, Real… Read More
The fabless revolution in the digital semiconductor industry is no more, with just a few integrated device manufacturers (IDMs) remaining on the playing field, it is now the normal way to do business. However, the learning curve for each new process node continues as it always has, with a host of new technical challenges for the … Read More
Early in my so-called EE career, I sat in a workshop led by the director of quality for the Ford truck plant in Louisville, KY, where “Quality is Job #1.” At that time, they were gaining experience in electronic control modules (ECMs) for fuel efficiency and emissions control. Who better to transfer the secrets of Crosby and Deming… Read More
The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively.… Read More
Taking a look at the coveted presentation slots at the CDNLive Conference next month you will see a presentation on Data Management for Mixed-Signal Designs by one of my favorite EDA companies, ClioSoft. Great software, great support, great people, and with customers that are willing to talk publicly about their tools and technology.… Read More
At the 2010 DACI moderated a panel session on SPICE and Fast SPICE circuit simulation, and one of the panelists was PierLuigi Dagliofrom STMicroelectronics. To get an update on SPICE circuit simulation at ST I read a PDF document at Mentor titled: Improving the Quality of SPICE Simulation Results with Eldo Premier at ST.
ST does … Read More
In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.
Rick… Read More
Repeat after me: SoCs are paperweights if they can’t be programmed. Succeeding with a new part today means supporting a robust developer program to attract and engage as many creatives as possible. NVIDIA has teamed up with Mentor Graphics in just such an adventure. If you read just the press release, you may have missed the real … Read More
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