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Calypto 2013 Report

Calypto 2013 Report
by Paul McLellan on 07-05-2013 at 5:48 am

Each year Calypto runs a survey of end-users. This year’s survey and report has two parts, power reduction and high level synthesis (HLS).

The topics covered are:

  • survey methodology and demographics
  • top methods used to reduce power
  • engineering time spent on specfiic RTL tasks to reduce power
  • plans to deploy RTL power reduction
Read More

Easy SystemC Debugging

Easy SystemC Debugging
by Randy Smith on 07-03-2013 at 7:00 pm

Electronic system design has been slowly migrating to higher level languages such as SystemC for more than a decade now. SystemC is an open source C++ library that has emerged as a standard for high-level design and system modeling. Writing code in SystemC has several advantages which I won’t elaborate on in this article, though… Read More


LicenseMonitor Users’ Group Silicon Valley

LicenseMonitor Users’ Group Silicon Valley
by Paul McLellan on 07-03-2013 at 3:03 am

If DAC is the most general event in our industry, then the LicenseMonitor Users’ Group Silicon Valley has to be one of the most focused. It was held back in May but one of the key presentations was Brian Janes of RTDA talking about what is new in the latest version of LicenseMonitor which is 2013.03.

Like a number of people at RTDA,… Read More


Full Chip IR Drop Analysis using Distributed Multi Processing

Full Chip IR Drop Analysis using Distributed Multi Processing
by Daniel Payne on 07-02-2013 at 6:56 pm

IR drop analysis across your board, package and SoC ensures that your Power Delivery Network (PDN) is robust, and that your system will function to spec. There are both static and dynamic approaches to IR drop analysis of a full-chip with billions of transistors, while the dynamic approach produces the most accurate results compared… Read More


When Atrenta celebrates with STM and CEA-Leti in Grenoble

When Atrenta celebrates with STM and CEA-Leti in Grenoble
by Eric Esteve on 07-01-2013 at 3:20 am

Grenoble is French city well-known within the Semiconductor industry to be one of the last location counting wafer fabs, not only in France but in fact in Europe. Back in the 70’s, under French government impulse, through the Commisariat à l’Energie Atomique (CEA) and the LETI subsidiary in charge of Electronic related research,… Read More


Workload-tuned cores seeing greater interest

Workload-tuned cores seeing greater interest
by Don Dingee on 06-30-2013 at 10:00 pm

Is it possible to design a processor with very high performance and low power consumption? To answer that, embedded illuminati are now focusing on designs tuned to specific workloads – creating a tailored processor that does a few things very efficiently, with nothing extra.… Read More


Today’s Program is Brought To You by the Letter A

Today’s Program is Brought To You by the Letter A
by Paul McLellan on 06-28-2013 at 9:09 pm

What do nVidia, Freescale and GlobalFoundries have in common? They are semiconductor companies? They are ARM licensees? They are doing 28nm chips? They all have the letter ‘a’ in their names?

All true, but that’s not what I was thinking of. But the letter ‘a’ is a clue since Apache (and Ansys) begin with ‘a’. All three companies have… Read More


Design Test and Regression Management of SoCs

Design Test and Regression Management of SoCs
by Daniel Payne on 06-28-2013 at 2:26 pm

Eric Peersfounded Missing Link tools in 2008 and his company was acquiredby Methodics in 2012, so I met with him at DAC to understand how their EDA tools for Design, Test and Regression Management are used in an SoC design.


Eric Peers, MethodicsRead More