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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4172
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4172
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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I could show you the FPGA, but then I’d have to configure you

I could show you the FPGA, but then I’d have to configure you
by Don Dingee on 10-31-2013 at 6:00 pm
Categories: Aldec, EDA, FPGA

One of the present ironies of the Internet of Things is as it seeks to connect every device on the planet, we are still designing those things with largely unconnected EDA tools. We may share libraries and source files on a server somewhere, but that is just the beginning of connection.

It is not surprising that synthesis tools from… Read More

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Device Noise Analysis of Switched-Cap Circuits

Device Noise Analysis of Switched-Cap Circuits
by Daniel Payne on 10-31-2013 at 12:00 pm
Categories: EDA

Switched-capacitor circuits are used in most CMOS mixed-signal ICs as:

  • Track and hold circuits
  • Integrators
  • Operational Amplifiers
  • Delta-sigma modulators


​Delta-Sigma Modulator: IEEE J. Solid-State Circuits, vol. 43, no. 12, pp 2601-2612, Dec. 2008… Read More

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M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013

M-PCIe, Data Converters, and USB 3.0 SSIC at IP SoC 2013
by Eric Esteve on 10-31-2013 at 9:38 am
Categories: EDA, Synopsys

Synopsys is taking IP-SOC 2013 seriously, as the company will hold several presentations, starting with a Keynote: “Virtual Prototyping – A Reality Check”, by Johannes Stahl, Director, Product Marketing, System-Level Solutions, Synopsys, highlighting current industry practice around putting virtual prototyping to work… Read More

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ARM in Samsung 14nm FinFET

ARM in Samsung 14nm FinFET
by Paul McLellan on 10-30-2013 at 4:28 pm
Categories: Arm, Cadence, EDA, Foundries, Samsung Foundry

I am at ARM TechCon today. One interesting presentation was made jointly between Samsung, Cadence and ARM themselves about developing physical libraries (ARM), a tool flow (Cadence) and test chips (Samsung). It was titled Samsung ARM and Cadence collaborate on the silicon-proven world first 14-nm FinFET Cortex-A7 ARM CPU and… Read More

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ARC EM SEP Processor, Safety Ready Solution for Automotive

ARC EM SEP Processor, Safety Ready Solution for Automotive
by Eric Esteve on 10-30-2013 at 5:24 am
Categories: EDA, Synopsys

If you are familiar with Processor IP core, you certainly know DesignWare ARC EM4 core, 32-bit CPU that SoC designers can optimize for a wide range of uses, and differentiate by using patented configuration technology to tailor each ARC core instance to meet specific performance, power and area requirements. If you develop a product… Read More

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Social Media at Mentor Graphics

Social Media at Mentor Graphics
by Daniel Payne on 10-29-2013 at 5:52 pm
Categories: EDA, Siemens EDA

You can often tell how important blogging and social media is to an EDA company by how much effort it takes to find their blog from the Home page. For the folks at Mentor Graphics I’d say that blogging is quite important, because it shows up as a top-level menu item. Notice also how important Twitter is, their latest tweets show… Read More

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Correct by Construction Semiconductor IP

Correct by Construction Semiconductor IP
by Daniel Payne on 10-29-2013 at 11:23 am
Categories: EDA, Fractal Technologies

Semiconductor IP re-use enables modern SoC designs to be realized in a timely fashion, yet with hundreds of IP blocks in a chip the chances are higher that an error in any IP block could cause the entire system to fail. At advanced nodes like 28nm and smaller, the number of Process, Voltage and Temperature (PVT) corners is increasing… Read More

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MEMS in The World of ICs – How to Quickly Verify?

MEMS in The World of ICs – How to Quickly Verify?
by Pawan Fangaria on 10-29-2013 at 10:00 am
Categories: Coventor, EDA

In the modern electronic world, it’s difficult to imagine any system working as a whole without MEMS (Micro-electromechanical Systems) such as pressure sensors, accelerometers, gyroscopes, microphones etc. working in sync with other ICs. Specifically in AMS (Analog Mixed-Signal) semiconductor designs, there can be significant… Read More

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TSMC ♥ Mentor (Calibre PERC)

TSMC ♥ Mentor (Calibre PERC)
by Daniel Nenni on 10-29-2013 at 8:00 am
Categories: EDA

As semiconductors become more integrated into our lives reliability is becoming a critical issue. As IP consumes more of our die, IP reliability is becoming a critical issue. As we pack more transistors into a chip, reliability is becoming a critical issue. As we move from 28nm to 20nm to 16nm, reliability is becoming a critical … Read More

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Diagnosing Double Patterning Violations

Diagnosing Double Patterning Violations
by Beth Martin on 10-28-2013 at 5:16 pm
Categories: EDA, Siemens EDA

I’ll bet you’ve read a bunch of stuff about double patterning, and you’re probably hoping that the design tools will make all your double patterning issues just go away. Well, the truth is that the foundries and EDA vendors have worked really hard to make that true.

However, for some critical portions of your design, there … Read More