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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4177
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4177
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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RTL Sign-off – At an Edge to become a Standard

RTL Sign-off – At an Edge to become a Standard
by Pawan Fangaria on 02-01-2014 at 10:00 am
Categories: EDA, TSMC


Ever since I have seen Atrenta’s SpyGlass platform providing a comprehensive set of tools across the semiconductor design paradigm, I felt the need for a common set of standards to evolve for sign-off at RTL level. Last December, when I read an EE Times articleof Piyush Sancheti, VP, Product Marketing at Atrenta, where he talks … Read More

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Power and Thermal Modeling Approach for Embedded and Automotive using ESL Tools

Power and Thermal Modeling Approach for Embedded and Automotive using ESL Tools
by Daniel Payne on 01-31-2014 at 7:04 pm
Categories: EDA

Did you know that an S-class Mercedes Benz can use 100 microprocessor-based electronic control units (ECUs) networking throughout the vehicle that run 20-100 million lines of code (Source: IEEE)?


2014 Mercedes-Benz CLA

Here’s a quick list of all the places that you will find software controlling hardware in an automobile:… Read More

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Update on a Space-Based Router for IC Design

Update on a Space-Based Router for IC Design
by Daniel Payne on 01-31-2014 at 11:50 am
Categories: Cadence, EDA

When I started my IC design career back in 1978 all IC routing was done manually, today however we have many automated approaches to IC routing that save time and do a more thorough job than manual routing. To get an update on space-based routers for IC design I connected with Yuval Shay at Cadence today. The basic idea behind a spaced-based… Read More

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Getting the best from MIPI IP Toolbox

Getting the best from MIPI IP Toolbox
by Eric Esteve on 01-31-2014 at 4:07 am
Categories: EDA, IP

The set of MIPI specifications has severely enlarged during the past year. This is a positive point, as the large set of specifications induces a wider choice, and a chip maker can decide to implement a complex specification to differentiate with competitors, or select a specification just tailored to support a basic architecture… Read More

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Untangling snags earlier and reducing area by 10%

Untangling snags earlier and reducing area by 10%
by Don Dingee on 01-30-2014 at 6:00 pm
Categories: EDA, Synopsys

The over 20 years of experience behind Synopsys Design Compiler is getting a new look for 2014, and we had a few minutes with Priti Vijayvargiya, director of product marketing for RTL synthesis, to explore what’s in the latest version of the synthesis tool.

Previewed today, Synopsys Design Compiler 2013.12 continues to target … Read More

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First Verdi Interoperability Apps Developer Forum

First Verdi Interoperability Apps Developer Forum
by Paul McLellan on 01-30-2014 at 11:47 am
Categories: EDA, Synopsys

Way back when SpringSoft was still SpringSoft and not Synopsys they launched Verdi Interoperability Apps (VIA) and an exchange for users to share them open-source style. I wrote about it back in 2011 when it was announced. Today, Synopsys announced the first developer forum for VIA. It will be held at SNUG on Wednesday, March 26,… Read More

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If requirements ask for it, it had better be there

If requirements ask for it, it had better be there
by Don Dingee on 01-29-2014 at 8:00 pm
Categories: Aldec, EDA, FPGA

Engineers are known for their attention to detail and precision in thinking, but sometimes still struggle during compliance audits. This is especially true the longer a list of requirements becomes, especially unstructured lists kept in spreadsheets and on Post-It notes.

It gets even more complicated, because in defense circles… Read More

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High Quality PHY IPs Require Careful Management of Design Data and Processes

High Quality PHY IPs Require Careful Management of Design Data and Processes
by Pawan Fangaria on 01-29-2014 at 10:05 am
Categories: Cliosoft, EDA

In last few years IP design has grown significantly compared to the rest of the semiconductor industry. There are newer IP start-ups opening across the world, particularly in India and China. Amid this rush, I wanted to understand the actual dynamics pushing this business and whether all of these IPs follow quality standards. … Read More

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CDNLive World Tour

CDNLive World Tour
by Paul McLellan on 01-28-2014 at 11:00 pm
Categories: Cadence, EDA

CDNLive is becoming a real worldwide event, starting in March in San Jose and ending in November in Tel Aviv, Israel.

The complete schedule is:

  • March 11-12th, Santa Clara, California
  • May 19th-21st, Munich, Germany
  • July 15th, Seoul, Korea
  • August 15th, Shanghai, China
  • August 7th, Hsinchu, Taiwan
  • August 11-12th, Bangalore, India
… Read More
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TSMC OIP presentations available!

TSMC OIP presentations available!
by Beth Martin on 01-27-2014 at 6:27 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference:

… Read More