The intricacies of analog IP circuit design have always required special consideration during physical layout. The need for optimum device and/or cell matching on critical circuit topologies necessitates unique layout styles. The complex lithographic design rules of current FinFET process nodes impose additional restrictions… Read More
Electronic Design Automation
Can Qualcomm avoid repeating Motorola’s fate?
NPR had an interesting guest this morning: Edward Luce, author of “Time to Start Thinking: America in the Age of Descent”. I’m not about to turn SemiWiki into a politics blog, but there is some precedent in the technology business. I’ve caught myself saying more than once recently that “Motorola is no longer the company I worked 14… Read More
Custom IC Design Flow with OpenAccess
Imagine being able to use any combination of EDA vendor tools for schematic capture, SPICE circuit simulation, layout editing, place & route, DRC, LVS and extraction. On the foundry side, how about creating just a single Process Development Kit (PDK), instead of vendor-specific kits. Well, this is the basic premise of a recent… Read More
VC Apps Tutorial at DVCon 2016
We might wish that all our design automation needs could be handled by pre-packaged vendor tool features available at the push of a button, but that never was and never will be the case. In the language of crass commercialism, there may be no broad market for those features, even though you consider that analysis absolutely essential.… Read More
Attending DAC in Austin for Free
I love getting a good deal, and free is always compelling, so how about attending DAC in Austin for free this year? Sound too good to be true? Thanks to the generosity of three EDA companies – ATop Tech, ClioSoft and OneSpin, now you can can attend parts of DAC for free by registering here. This is now the 8th year that the I LOVE DAC… Read More
Software-Driven Verification and Portable Stimulus
I was at every single lunch at DVCon, not because the food was that great (it wasn’t bad) but because the topics were all interesting. The Wednesday lunch, hosted by Cadence, was a panel on software-driven verification and portable stimulus, moderated by Frank Schirrmeister (a different role for Frank – he’s usually a panel member… Read More
Speaking about the Internet of Trust on April 21
Five minutes to ruin a reputation built over 20 years, as Warren Buffett put it, holds true in personal relationships. On the Internet of Things, reputations can disappear in five seconds. How do we move from merely intelligent Things to a level where devices have to be Trusted?… Read More
Mentor Extends Verification Offering!
With verification consuming more and more of the design cycle and the increasingly complex industry standard interfaces that are now common place, Verification IP (VIP) is again a trending topic. Back in my IP days the age old question was: Is it better to use VIP from the IP vendor? Because you know it will work, right? Or is it better… Read More
Apple Protects Its Designs With Custom Silicon And You Can Too
In the February 22-28 issue of Bloomberg Businessweek magazine, Johny Srouji, Apple’s senior vice president for hardware technologies, discusses Apple’s winning strategy of owning its own silicon. It began with the acquisition a Silicon Valley chip startup called P.A. Semi in April of 2008 and since then, Apple has never looked… Read More
Is Smart Bluetooth de facto standard for IoT Wearable, Beacons, Fitness and Health ?
Synopsys launch BTLE PHY IP, qualified by the Bluetooth Special Interest Group (SIG) and meeting compliance with the Bluetooth® Smart v4.2 specification. The company has built a partnership with Mindtree to provide a complete solution, integrating Synopsys’ Bluetooth Smart PHY IP and Mindtree’s production-proven BlueLitE… Read More


AI RTL Generation versus AI RTL Verification