whitepaper timing semiwiki ad
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4384
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4384
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

DAC 2016 – Register Now

DAC 2016 – Register Now
by Bernard Murphy on 05-16-2016 at 7:00 am

DAC is again going to be in Austin (reason enough to go), from June 6[SUP]th[/SUP]-8[SUP]th[/SUP] for the main event. A number of events caught my eye:

  • Monday AM – custom hardware for algorithmic trading. If you want to know more about FinTech (technology for finance) this could be for you
  • Another Monday morning session on Linux
Read More

The Emerging Importance of Parallel SPICE

The Emerging Importance of Parallel SPICE
by admin on 05-15-2016 at 7:00 am

SPICE simulation is the workhorse tool for custom circuit timing validation and electrical analysis. As the complexity of blocks and macros has increased in advanced process nodes — especially with post-layout extraction parasitic elements annotated to the circuit netlist — the model size and simulation throughput… Read More


AMD Forms China X86 Server Chip Joint Venture

AMD Forms China X86 Server Chip Joint Venture
by Patrick Moorhead on 05-13-2016 at 4:00 pm

We have written a lot of research and notes about the China server market and their unique needs as it relates to security and intellectual property and the ways western server OEMs and chipmakers like Intel, Advanced Micro Devices, ARM Holdings, Qualcomm and IBM’s OpenPOWER are addressing the challenge.

Basically, China wants… Read More


Getting Low Power Design Right in Mixed Signal Designs

Getting Low Power Design Right in Mixed Signal Designs
by Bernard Murphy on 05-12-2016 at 4:00 pm

Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More


Channel Operating Margin (COM) — A Standard for SI Analysis

Channel Operating Margin (COM) — A Standard for SI Analysis
by Tom Dillinger on 05-12-2016 at 12:00 pm

There’s an old adage, attributed to renowned computer scientist Andrew Tannenbaum, one that perhaps only engineers find amusing: “The nice thing about standards is that you have so many to choose from.” Nevertheless, IEEE standards arise from customer requirements in the electronics industry. Many relate… Read More


CEO Insight: Transformation of Vayavya Labs into System Design Automation

CEO Insight: Transformation of Vayavya Labs into System Design Automation
by Pawan Fangaria on 05-12-2016 at 7:00 am

With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More


Why NXP is Moving to FD-SOI (Part II)

Why NXP is Moving to FD-SOI (Part II)
by Ron Martino on 05-10-2016 at 2:00 pm

At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI. As noted in part I of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable… Read More


TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes

TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
by Daniel Nenni on 05-10-2016 at 12:00 pm

Being that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from Solido:… Read More


Why is NXP Moving to FD-SOI?

Why is NXP Moving to FD-SOI?
by Ron Martino on 05-08-2016 at 11:00 am

The latest generations of power efficient and full-featured applications processors in NXP’s very successful and broadly deployed i.MX platform are being manufactured on 28nm FD-SOI. The new i.MX 7 series leverages the 32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets, where… Read More


One FPGA synthesis flow for different IP types

One FPGA synthesis flow for different IP types
by Don Dingee on 05-06-2016 at 4:00 pm

Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?

There is a compelling argument to use each FPGA vendor’s… Read More