Banner Electrical Verification The invisible bottleneck in IC design updated 1
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ClioSoft & DAC : Booth 613 – Collaborative Design, Design Data & IP Management and Design Reuse

ClioSoft & DAC : Booth 613 – Collaborative Design, Design Data & IP Management and Design Reuse
by Mitch Heins on 06-06-2017 at 7:00 am


It’s time again to gather for the next Design Automation Conference (DAC). This will be the 54[SUP]th[/SUP] such meeting and this year it runs from June 19[SUP]th[/SUP] – 21[SUP]st[/SUP] in the Live Music Capital of the World, Austin Texas. Put on your best duds, boots and cowboy hat and make your way to Texas.

While you are there … Read More


Tools for Advanced Packaging Design Follow Moore’s Law, Too!

Tools for Advanced Packaging Design Follow Moore’s Law, Too!
by Tom Dillinger on 06-05-2017 at 9:00 am

There is an emerging set of advanced packaging technologies that enables unique product designs, with the capability to integrate multiple die, from potentially heterogeneous technologies. These “system-in-package” (SiP) offerings provide architects with the opportunity to optimize product performance, power, cost,… Read More


An InFormal Chat

An InFormal Chat
by Bernard Murphy on 06-05-2017 at 7:00 am

Any sufficiently advanced technology is indistinguishable from magic, as the saying goes. Which is all very well when the purpose is entertainment or serving the arcane skills of a select priesthood, but it’s not a good way to grow a market. Then you want to dispel the magic aura, make the basic mechanics more accessible to a wider… Read More


Margin Call

Margin Call
by Bernard Murphy on 06-04-2017 at 7:00 am

A year ago, I wrote about Ansys’ intro of Big Data methods into the world of power integrity analysis. The motivation behind this advance was introduced in another blog, questioning how far margin-based approaches to complex multi-dimensional analyses could go. An accurate analysis of power integrity in a complex chip should… Read More


Is ARC HS4xD Family More a CPU or DSP IP Core?

Is ARC HS4xD Family More a CPU or DSP IP Core?
by Eric Esteve on 06-02-2017 at 4:00 pm

When I had to define the various IP categories (processor, analog & mixed-signal, wired interfaces, etc.) to build the Design IP Report, I scratched my head for a while about the processor main category: how to define the sub-categories? Not that long ago, it was easy to identify a CPU IP core and a DSP IP core. As of today, if a DSP… Read More


Getting to IP Functional Signoff

Getting to IP Functional Signoff
by Bernard Murphy on 06-01-2017 at 7:00 am

In the early days of IP reuse and platform-based design there was a widely-shared vision of in-house IP development teams churning out libraries of reusable IP, which could then be leveraged in many different SoC applications. This vision was enthusiastically pursued for a while; this is what drove reusability standards and … Read More


RTL Correct by Construction

RTL Correct by Construction
by Bernard Murphy on 05-31-2017 at 7:00 am

Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc)… Read More


Consolidation and Design Data Management

Consolidation and Design Data Management
by Bernard Murphy on 05-30-2017 at 7:00 am

Consensia, a Dassault Systemès channel partner, recently hosted a webinar on DesignSync, a long-standing pillar of many industry design flows (count ARM, Qualcomm, Cavium and NXP among their users). A motivation for this webinar was the impact semiconductor consolidation has had on the complexity of design data management,… Read More