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Electronic Design Automation
Advanced packaging technology is enabling “More Than Moore” scaling of heterogeneous technology die. At the recent EDPS Symposium in Milpitas, Craig Hillman, Director of Product Development, DfR Solutions, at ANSYS gave a compelling presentation, “Reliability Challenges in Advanced Packaging”. The key takeaway messages… Read More
Most EDA tools started out running on mainframe computers, then minicomputers, followed by workstations and finally desktop PCs running Linux. If your SoC design team is working on a big chip with over a billion transistors, then your company likely will use a compute farm to distribute some of the more demanding IC jobs over lots… Read More
Flash memory has become ubiquitous, so much so that it is easy to forget what life before it was like. Large scale non-volatile storage was limited spinning disks, which were bulky, power hungry and unreliable. With NAND Flash, we have become used to carrying many gigabytes around with us all the time in the form of cell phones, USB… Read More
Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More
I wrote about Cadence AI IP not long ago when I covered the Cadence Automotive Summit at the end of July (Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving, Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear). One of those two blogs remains one of my most widely … Read More
The transition to the digital age from a mostly analog world really began with the invention of the A-to-D and D-to-A converters. However scalar processors can easily be overwhelmed by the copious data produced by something as simple as an audio stream. To solve this problem and to really jumpstart the digital age, the development… Read More
In a joint presentation given by Samsung, Arm, and Cadence at the Arm TechCon event on October 9, 2019, Cadence showed some results and explained its collaboration project used to implement the new Arm Hercules CPU on Samsung’s advanced 5LPE process. I do not want to minimize the significance of Samsung’s and Arm’s participation… Read More
My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical… Read More
If you have ever watched an experienced glass blower, your first thought is that they make it look so easy. I have had the opportunity to blow glass, and I can tell you that it is a constant struggle against temperature, time and muscles to get the glass to do anything like what you want. This is akin to what is required to take the elements… Read More
Verifying a design for functional safety requirements for an IP or SoC per ISO 26262 is a complex process that can’t be encapsulated in one tool. Process complexities depend on whether the Tier1 or OEM is targeting safety-levels ASIL-A , B, C or D, where ASIL-D applies to anything truly safety-critical such as airbag controls or … Read More
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