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Electronic Design Automation
The current Coronavirus crisis is inflicting a lot of pain on people, companies, and governments. I hope I am not getting in trouble with my reasoning, but if you look closely, there are also some “positives” to the Covid-19 crisis.
– It is stress-testing our infrastructure and telling us where we need to improve – as country,… Read More
Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.
The Innovation
This month’s pick is Which Software … Read More
The road to a truly usable design management solution for electronic design has been a long and twisty one. Initially just handling EDA tool data was a struggle, let alone addressing mutli-user and multi-site needs. Of course, all along every EDA tool development company was internally using software revision control, which … Read More
Tom Fitzpatrick, a Strategic Verification Architect at Mentor, a Siemens Business, has worked on IEEE and Accellera standards like Verilog 1364, System Verilog 1800, UVM 1800.2 and is Vice Chair of the Portable Stimulus working group, so when I heard that he was doing a webinar on how PSS can be used to create better stimulus for … Read More
The foundation of SemiWiki.com has always been to transition live semiconductor related events to an easy to digest digital format via a worldwide online semiconductor community. SemiWiki is staffed by working semiconductor professionals that transform live events, press releases, whitepapers, webinars and other collateral… Read More
Over the years SerDes (serializer/deserializer) based connections have proliferated into just about every connection within and among computing systems. Years ago, parallel interfaces were the most common method of moving data, but issues of signal integrity, synchronization and power simply became too much for the required… Read More
Design complexities in reset, like everything else in big SoC designs, has become incredibly complex, for all sorts of reasons. Long, long ago reset was something you just did once, when you turned the power on. Turn on, then hold reset for some amount of time until everything is in a known starting state, and off you go. Nice and simple.… Read More
As I originally reported a few weeks ago, the Jim Hogan fireside chat with Methodic’s CEO and founder Simon Butler was moved to a virtual event on May 1. The event was produced by the Electronic System Design (ESD) Alliance, a SEMI Strategic Technology Community. Bob Smith, executive director of ESDA, moderated the event. I am happy… Read More
Based on what I’m seeing, I believe Cadence is looking at the world a bit differently these days. I first reported about their approach to machine learning for EDA in March, and then there was their white paper about Intelligent System Design in April. It’s now May, and Cadence is shaking things up again with a new white paper entitled… Read More
I had the opportunity to attend a ClioSoft webinar recently on the topic of IP traceability. ClioSoft provides a broad range of tools for design data management and IP reuse. Entitled The New Trend in IP Traceability that IP Developers and Design Managers Rely On, the webinar was presented by Karim Khalfan, director of applications… Read More
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AI Bubble?