SILVACO 073125 Webinar 800x100
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EDA

Electronic Design Automation

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Speeding up Circuit Simulation using a GPU Approach

Speeding up Circuit Simulation using a GPU Approach
by Daniel Payne on 08-22-2019 at 10:00 am
Categories: EDA, Empyrean, Events

ALPS-GT

The old adage that “Time is Money” certainly rings true in the semiconductor world where IC designers are being challenged with getting their new designs to market quickly, and correctly in the first spin of silicon. Circuit designers work at the transistor-level, and circuit simulation is one of the most time-consuming… Read More

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Making pre-Silicon Verification Plausible for Autonomous Vehicles

Making pre-Silicon Verification Plausible for Autonomous Vehicles
by Daniel Payne on 08-20-2019 at 10:00 am
Categories: Automotive, EDA, Siemens EDA

AV diagram

I love reading about the amazing progress of autonomous vehicles, like when Audi and their A8 model sedan was the first to reach Level 3 autonomy, closely followed by Tesla at Level 2, although Tesla gets way more media attention here in the US. A friend of mine bought his wife a car that offers adaptive cruise control with auto-braking,… Read More

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Xilinx on ANSYS Elastic Compute for Timing and EM/IR

Xilinx on ANSYS Elastic Compute for Timing and EM/IR
by Bernard Murphy on 08-20-2019 at 5:00 am
Categories: Ansys, Inc., EDA, FPGA, Xilinx

RedHawk-SC

I’m a fan of getting customer reality checks on advanced design technologies. This is not so much because vendors put the best possible spin on their product capabilities; of course they do (within reason), as does every other company aiming to stay in business. But application by customers on real designs often shows lower performance,… Read More

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Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear

Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear
by Randy Smith on 08-16-2019 at 10:00 am
Categories: Cadence, IP

It seems every day we see a new article (or ten) on autonomous driving. It is an especially hot topic, and it will happen someday. For now, we can dream about it, and many people are working on it. But for the present, the technology in a car that commands my attention is audio. I’ve been a musician since 4th grade. I still perform occasionally… Read More

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Can a hierarchical Test flow be used on a flat design?

Can a hierarchical Test flow be used on a flat design?
by Tom Simon on 08-15-2019 at 10:00 am
Categories: EDA, Siemens EDA

It is pretty common for physical layout to work from a flattened hierarchy for blocks or even full chips, even though the front-end design starts with a hierarchical representation. This was not always the case. Way back when, the physical layout matched the logical hierarchy during the design process. Of course, this led to all… Read More

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Mentor-Tanner Illuminate MEMS Sensing, Fusion

Mentor-Tanner Illuminate MEMS Sensing, Fusion
by Bernard Murphy on 08-14-2019 at 6:00 am
Categories: AI, Automotive, EDA, Siemens EDA
2 Comments

I enjoy learning and writing about new technologies closely connected to our personal and working lives (the kind you could explain to your Mom or a neighbor). So naturally I’m interested in AI, communication and security as applied to the home automation, transportation, virtual, augmented and mixed reality, industry and so… Read More

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Accelerate Your Early Design Recon

Accelerate Your Early Design Recon
by Alex Tan on 08-13-2019 at 6:00 am
Categories: Siemens EDA

A product launch nowadays demands shorter runway. SoC designers challenges are not so much in facing the unavailability of proven design capture methodologies or IP’s that could satisfy their product requirements, but more so in orchestrating the integration of all those components to deliver the targeted functionalities… Read More

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Webinar: Designing Complex SoCs and Dealing with Multiple File Formats

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats
by Daniel Payne on 08-12-2019 at 10:00 am
Categories: Concept Engineering, EDA, Events

StarVision Pro

In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:

  • Transistor-level , SPICE
  • Interconnect parasitics, SPEF
  • Gate and RTL, Verilog, VHDL

Even with standard file formats, designers still have to traverse the hierarchy to find out… Read More

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Adding CDM Protection to a Real World LNA Test Case

Adding CDM Protection to a Real World LNA Test Case
by Tom Simon on 08-06-2019 at 6:00 am
Categories: EDA, Events, Magwel

In RF designs Low Noise Amplifiers (LNA) play a critical role in system operation. They simultaneously need to be extremely sensitive and noise free, yet also must be able to withstand strong signal input without distortion. LNA designers often struggle to meet device performance specifications. Their task is further complicated… Read More

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GPU-Powered SPICE – Understanding the Cost

GPU-Powered SPICE – Understanding the Cost
by Daniel Nenni on 08-01-2019 at 10:00 am
Categories: EDA, Empyrean, Events
2 Comments

To deploy a GPU-based SPICE solution, you need to understand the costs involved. To get your hands on this new report analyzing this specific issue, all you need to do is attend Empyrean’s upcoming webinar, “GPU-Powered SPICE:  The Way Forward for Analog Simulation,” which will be held on Thursday, August 8, 2019, at 10:00 am (PDT).… Read More