I attended a session on 2.5D silicon interposer analysis at DesignCon 2020. Like many presentations at this show, ecosystem collaboration was a focus. In this session, Jinsong Hu (principal application engineer at Cadence) and Yongsong He (senior staff engineer at Enflame Tech) presented approaches for interposer power modeling… Read More
Electronic Design Automation
Executive Interview: Howie Bernstein of HCL
Howie began his career at Digital Equipment Corporation working on real-time device drivers, but within a few years started working at the other end of the stack with one of the pioneering electronic mail systems. Since then, Howie has worked on developing systems involving electronic mail, workflow processing, configuration… Read More
Verification, RISC-V and Extensibility
RISC-V is obviously making progress. Independent of licensee signups and new technical offerings, the simple fact that Arm is responding – in fundamental changes to their licensing model and in allowing custom user extensions to the instruction set – is proof enough that they see a real competitive threat from RISC-V.
Which all… Read More
Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes
This year is the 25th anniversary for DesignCon. The show has changed a lot over the years. Today, it’s a vibrant showcase of all aspects of advanced product design – from ICs to boards to systems. The show floor reflects the diverse ecosystem. If you missed it this year, definitely plan to go next year.
The DesignCon technical program… Read More
Bringing Hierarchy to DFT
Hierarchy is nearly universally used in the SoC design process to help manage complexity. Dealing with flat logical or physical designs proved unworkable decades ago. However, there were a few places in the flow where flat tools continued to be used. Mentor lead the pack in the years around 1999 in helping the industry move from … Read More
Formal and High-Level Synthesis
Formal verification has made significant inroads in RTL and gate-level verification because it provides complementary strengths to conventional dynamic verification methods; using both provides higher levels of coverage and confidence in the correctness of an implementation. I haven’t heard as much about formal use in … Read More
Innovation in Verification – January 2020
I’m kicking off a blog series which should appeal to many of us in functional verification. Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan (angel investor and board member extraordinaire) and I (sometime blogger) like to noodle from time to time on papers and other verification articles which inspire us.… Read More
Saving Time in Physical Verification by Reusing Metadata
Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:
- Physical validation
- Circuit validation
- Reliability verification
This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More
PAVE360 is Fully Armed!
Siemens today announced a partnership with Arm to “accelerate the future of mobility by redefining design capabilities for complex electronic systems”. I spent time with David Fritz to understand what this really means. You may remember David from our webinar PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle… Read More
Photonics Come into Focus: 2020 Predictions
In the past, I’ve focused my annual predictions on electronics – ICs and EDA – but recently I’ve turned my focus to photonics, so my 2020 predictions are primarily in this area.
Historically, photonics has been the Gallium Arsenide of technologies; it was, is and always will be the technology of the future. Analysts have forever … Read More
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