WP_Term Object
(
    [term_id] => 42
    [name] => AMIQ EDA
    [slug] => amiq-eda
    [term_group] => 0
    [term_taxonomy_id] => 42
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 24
    [filter] => raw
    [cat_ID] => 42
    [category_count] => 24
    [category_description] => 
    [cat_name] => AMIQ EDA
    [category_nicename] => amiq-eda
    [category_parent] => 157
    [is_post] => 
)
            
AMIQ Banner
WP_Term Object
(
    [term_id] => 42
    [name] => AMIQ EDA
    [slug] => amiq-eda
    [term_group] => 0
    [term_taxonomy_id] => 42
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 24
    [filter] => raw
    [cat_ID] => 42
    [category_count] => 24
    [category_description] => 
    [cat_name] => AMIQ EDA
    [category_nicename] => amiq-eda
    [category_parent] => 157
    [is_post] => 
)

What’s New with UVM and UVM Checking?

What’s New with UVM and UVM Checking?
by Daniel Nenni on 06-30-2021 at 6:00 am

UVM and UVM Checking

About once a quarter, I touch base with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to see what’s new with the company, products, and users. Sometimes he surprises me, as he did earlier this year when he mentioned that their tools check about 150 rules for non-standard constructs in SystemVerilog and VHDL. When we talked … Read More


Why Would Anyone Perform Non-Standard Language Checks?

Why Would Anyone Perform Non-Standard Language Checks?
by Daniel Nenni on 03-29-2021 at 6:00 am

Non Standard

The other day, I was having one of my regular chats with Cristian Amitroaie, CEO and co-founder of AMIQ EDA. One of our subjects was a topic that we discussed last year, the wide range of languages and formats that chip design and verification engineers use these days. AMIQ EDA has put a lot of effort into adding support for many of these… Read More


Does IDE Stand for Integrated Design Environment?

Does IDE Stand for Integrated Design Environment?
by Daniel Nenni on 12-21-2020 at 6:00 am

SemiWiki2 design 1

As regular readers may know, every few months I check in with Cristian Amitroaie, CEO of AMIQ EDA, to see what’s new with the company and their products. In our posts so far this year we’ve focused on verification, and now I’m wondering how an integrated development environment (IDE) provides benefits to designers. They work on huge… Read More


Don’t You Forget About “e”

Don’t You Forget About “e”
by Daniel Nenni on 09-25-2020 at 10:00 am

e Flow Vert

I imagine that the title of this post will remind many of 80s synth-pop, or perhaps the movie The Breakfast Club. But my topic is the venerable hardware verification language (HVL) known simply as e. It has quite an interesting history and it played a key role in the development of the modern testbench methodology that most chip verification… Read More


The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am

SemiWiki article

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More


An Important Step in Tackling the Debug Monster

An Important Step in Tackling the Debug Monster
by Daniel Nenni on 02-28-2020 at 6:00 am

AMIQ EDA Compare Report SemiWiki

If you’ve spent any time at all in the semiconductor industry, you’ve heard the statement that verification consumes two-thirds or more of the total resources on a chip project. The estimates range up to 80%, in which case verification is taking four times the effort of the design process. The exact ratio is subject to debate, but… Read More


Debugging Hardware Designs Using Software Capabilities

Debugging Hardware Designs Using Software Capabilities
by Daniel Nenni on 12-20-2019 at 6:00 am

Every few months, I touch base with Cristian Amitroaie, CEO of AMIQ EDA, to learn more about how AMIQ is helping hardware design and verification engineers be more productive. Quite often, his answers surprise me. When he started describing their Design and Verification Tools (DVT) Eclipse Integrated Development Environment… Read More


Automatic Documentation Generation for RTL Design and Verification

Automatic Documentation Generation for RTL Design and Verification
by Daniel Nenni on 09-16-2019 at 10:00 am

Ask any hardware or software engineer working on a product, and they will tell you that writing documentation is a pain. Customers have high expectations for user manuals and reference guides, usually requiring a team of technical writers to satisfy their requirements. In order to meet time-to-market deadlines, documentation… Read More


An Important Next Step for Portable Stimulus Adoption

An Important Next Step for Portable Stimulus Adoption
by Daniel Nenni on 07-02-2019 at 5:00 am

Portable stimulus has been a hot topic for a couple of years in the EDA and semiconductor industries. Many observers see this approach as the next major advance in verification beyond the Universal Verification Methodology (UVM), and the next step higher in abstraction for specifying verification intent. The basic idea is to … Read More


With Great Power Comes Great Visuality

With Great Power Comes Great Visuality
by Daniel Nenni on 03-29-2019 at 12:00 am

Every system-on-chip (SoC) designer worries about power. Many widely used electronics applications run on batteries, including smartphones, tablets, autonomous vehicles, and many Internet-of-Things (IoT) devices. Even “big iron” products such as network switches and compute servers must be careful when it comes to power… Read More