Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Video EP12: How Mach42 is Changing Analog Verification with Antun Domic

Video EP12: How Mach42 is Changing Analog Verification with Antun Domic
by Daniel Nenni on 11-21-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Antun Domic, who discusses Mach42’s work on AI and analog verification. Antun covers many aspects of analog/AMS verification and how Mach42’s unique AI-fueled approach provides significant benefits. He explains the balance of speed … Read More


WEBINAR: Is Agentic AI the Future of EDA?

WEBINAR: Is Agentic AI the Future of EDA?
by Admin on 11-20-2025 at 6:00 am

NetApp Cadence Webinar Banner

The semiconductor industry is entering a transformative era, and few trends are generating more discussion or confusion than Agentic AI. From autonomous design exploration to next-generation verification strategies, Agentic AI promises dramatic changes in how chips are conceived, validated, and delivered. But as with … Read More


FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges

FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges
by Daniel Nenni on 11-19-2025 at 10:00 am

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Modern chip design verification often encounters challenges when connecting peripherals, primarily due to drastic differences in operating speed or hardware limitations. Designs running on hardware emulators or FPGA prototyping platforms typically operate at clock frequencies of tens of megahertz, and in some cases even… Read More


An Insight into Building Quantum Computers

An Insight into Building Quantum Computers
by Bernard Murphy on 11-19-2025 at 6:00 am

Quantum processor courtesy IBM

Given my physics background I’m ashamed to admit I know very little about quantum computers (QC) though I’m now working to correct that defect. Like many of you I wanted to start with the basics: what are the components and systems in the physical implementation of a quantum “CPU” and how do they map to classical CPUs? I’m finding the… Read More


I Have Seen the Future with ChipAgents Autonomous Root Cause Analysis

I Have Seen the Future with ChipAgents Autonomous Root Cause Analysis
by Mike Gianfagna on 11-18-2025 at 10:00 am

I Have Seen the Future with ChipAgents Autonomous Root Cause Analysis

I have seen a lot of EDA tool demos in my time. More than I want to admit. The perceived quality of the demo usually came down to a combination of the speed of the tool, quality of results and the ease of navigating through the graphical user interface. For the last item, how easy the interface was on the eyes, how clear were the relationships… Read More


Revolution EDA: A New EDA Mindset for a New Era

Revolution EDA: A New EDA Mindset for a New Era
by Admin on 11-17-2025 at 6:00 am

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Murat Eskiyerli, PhD, is the founder of Revolution EDA  

Modern software development environments have evolved dramatically. A developer can download Visual Studio Code, install a few plugins, and be productive within minutes. The cost? Perhaps a few hundred dollars per month for cloud development resources. Compare that toRead More


WEBINAR: Revolutionizing Electrical Verification in IC Design

WEBINAR: Revolutionizing Electrical Verification in IC Design
by Daniel Nenni on 11-16-2025 at 10:00 am

Electrical Verification – The invisible bottleneck in IC design 2

In the complex world of IC design, electrical verification has emerged as a critical yet often overlooked bottleneck. Aniah’s upcoming webinar on December 4, 2025, titled “Electrical Verification: The Invisible Bottleneck in IC Design,” sheds light on this issue, introducing their groundbreaking OneCheck® solution. … Read More


Podcast EP317: A Broad Overview of Design Data Management with Keysight’s Pedro Pires

Podcast EP317: A Broad Overview of Design Data Management with Keysight’s Pedro Pires
by Daniel Nenni on 11-14-2025 at 10:00 am

Daniel is joined by Pedro Pires, a product and technology leader with a strong background in IP and data management within the EDA industry. Currently a product manager at Keysight Technologies, he drives the roadmap for the AI-driven data management solutions. Pedro’s career spans roles in software engineering and data science… Read More


Hierarchically defining bump and pin regions overcomes 3D IC complexity

Hierarchically defining bump and pin regions overcomes 3D IC complexity
by Admin on 11-13-2025 at 8:00 am

connectivity in a hierarchical IC package floorplan

By Todd Burkholder and Per Viklund, Siemens EDA

The landscape of advanced IC packaging is rapidly evolving, driven by the imperative to support innovation on increasingly complex and high-capacity products. The broad industry trend toward heterogeneous integration of diverse die and chiplets into advanced semiconductor… Read More


CDC Verification for Safety-Critical Designs – What You Need to Know

CDC Verification for Safety-Critical Designs – What You Need to Know
by Mike Gianfagna on 11-13-2025 at 6:00 am

CDC Verification for Safety Critical Designs – What You Need to Know

Verification is always a top priority for any chip project. Re-spins result in lost time-to-market and significant cost overruns. Chip bugs that make it to the field present another level of lost revenue, lost brand confidence and potential costly litigation. If the design is part of the avionics or control for an aircraft, the… Read More