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Threads

ChipAgents AI Verification Webinar Banner

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Podcast EP378: An Overview of the 2026 Wilson Research Group Functional Verification Study with Harry Foster

Podcast EP378: An Overview of the 2026 Wilson Research Group Functional Verification Study with Harry Foster
by Daniel Nenni on 11-13-2026 at 12:00 pm
Categories: EDA, Siemens EDA

Daniel is joined by Harry Foster, Chief Scientist of Veriﬁcation for Siemens Digital Industries Software. Harry is also the Co-Founder and Executive Editor for the Veriﬁcation Academy. Harry served as the 2021 Design Automation Conference General Chair and is currently serving as a Past Chair. He holds multiple patents and … Read More

November 13, 2026November 13, 2026

CEO Interview with Sergiy Nesterenko of Quilter on AI PCB Layout

CEO Interview with Sergiy Nesterenko of Quilter on AI PCB Layout
by Daniel Nenni on 11-13-2026 at 9:00 am
Categories: CEO Interviews, EDA, Quilter

Sergiy Nesterenko is founder and CEO of Quilter, which builds physics-driven AI for printed circuit board (PCB) layout. He triple majored in mathematics, physics, and chemistry at UC Berkeley and worked in the electromagnetic interference and compatibility (EMI/EMC) group at SpaceX during the early Falcon 9 era before founding… Read More

November 12, 2026November 12, 2026

CTO Interview With Juan Rey, senior VP and general manager of Calibre and CTO of Siemens EDA

CTO Interview With Juan Rey, senior VP and general manager of Calibre and CTO of Siemens EDA
by Daniel Nenni on 11-12-2026 at 12:00 pm
Categories: 3D IC, EDA, Siemens EDA

By Juan Rey, Chief Technology Officer, Siemens

Juan Rey is Head of Technology and Innovation for Electronic Design Automation (EDA) at Siemens and Vice President and General Manager for Calibre. He joined Mentor Graphics, now Siemens EDA, in 2001 and led engineering, research, development, and quality for Calibre before retiring… Read More

November 11, 2026November 11, 2026

CTO Interview Kevin Robinson, VP of Operations, yieldHUB

CTO Interview Kevin Robinson, VP of Operations, yieldHUB
by Daniel Nenni on 11-11-2026 at 12:00 pm
Categories: EDA, yieldHUB

Kevin Robinson is VP of Operations at yieldHUB, where he leads global operations, program delivery, and customer execution. He oversees structured onboarding, customer delivery, and the scalability of yieldHUB’s operations worldwide.

Kevin brings more than 25 years of semiconductor experience across product and test engineering.… Read More

November 10, 2026November 11, 2026

CXO Interview with Solaiman Rahim of ChipAgents

CXO Interview with Solaiman Rahim of ChipAgents
by Daniel Nenni on 11-10-2026 at 12:00 pm
Categories: CEO Interviews, ChipAgents AI, EDA

Dr. Solaiman Rahim is a multidisciplinary technology executive with over 25 years of experience driving innovation in the chip automation space at the intersection of systems, semiconductors, high-performance computing, and AI. As Chief Product Officer at ChipAgents, he leads the scaling of the Agentic and Native AI platform… Read More

November 10, 2026November 10, 2026

Three-Dimensional Chess Anyone? The Challenges of Power Integrity for Multi-Die Designs

Three-Dimensional Chess Anyone? The Challenges of Power Integrity for Multi-Die Designs
by Mike Gianfagna on 11-10-2026 at 6:00 am
Categories: 3D IC, AI, EDA, Synopsys

Power integrity has been a substantial design challenge for a long time. In the multi-die era, the problems associated with EMIR analysis must now move beyond the chip to consider interactions across the entire stack. The effects to be analyzed span a multi-dimensional, multi-material space. The graphic at the top of this post… Read More

November 9, 2026November 10, 2026

Golden Testcases You Can Check With a Calculator

Golden Testcases You Can Check With a Calculator
by Admin on 11-09-2026 at 10:00 am
Categories: EDA

Two timing tools that agree can still both be wrong. A small testcase where you can re-derive every printed digit by hand shows that the engine is correct, and when it isn’t, it shows which term is wrong.

By Dr. Sameer Pawanekar, Founder & CEO, Ramtera Inc.

The problem: agreement is not correctness

New static timing engines, and… Read More

November 9, 2026November 10, 2026

Curvilinear OPC and next-gen photomask optimization

Curvilinear OPC and next-gen photomask optimization
by Admin on 11-09-2026 at 8:00 am
Categories: EDA, Siemens EDA

A vector-based approach for semiconductor manufacturing

By Sagar Saxena is a Senior Product Engineer at Siemens EDA

Curvilinear OPC transforms advanced semiconductor manufacturing

Modern semiconductor manufacturing is experiencing a fundamental shift in the way photomasks are created and optimized. As the industry pushes… Read More

November 6, 2026November 4, 2026

ChipNexus Brings Agentic AI into Established Analog Design Flows

ChipNexus Brings Agentic AI into Established Analog Design Flows
by Daniel Nenni on 11-06-2026 at 10:00 am
Categories: ChipNexus, EDA

ChipNexus has introduced its NEX Analog Agent, bringing conversational automation to analog engineering workflows built around Cadence Virtuoso, Spectre simulation and Siemens Calibre physical verification. Available now, the software operates with customers’ installed tools, licenses and process design kits, giving… Read More

November 6, 2026November 13, 2026

CEO Interview with Jun Yuan of Arcas-Tech

CEO Interview with Jun Yuan of Arcas-Tech
by Daniel Nenni on 11-06-2026 at 6:00 am
Categories: CEO Interviews, EDA

Arcas tech Proving the future of silicon

JUN YUAN BIO
◆Engineer for chip design, simulation, and P&R at AMD; Senior Engineer for chip verification (emulation, equivalence checking, formal verification) at Motorola since 1992.
◆Held R&D and technical management roles in formal verification EDA at Verplex, Jasper, and Cadence since 2003.
◆Founded Arcas-tech… Read More

The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
would you like to design a Soc Chip by AI?

— beck999 on November 9, 2026
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
Great article, and thanks for sharing. The point about seams hit home. Every vendor interface is a place where delays…

— Joel Jorgensen on November 5, 2026
Intel’s Tiny Bridges Could Lead to Very Big Paychecks
When will Intel start to have sales revenue on this?

— Mark Webb on November 2, 2026
High-NA’s Obituary Was Premature
Within each EUV user company, there must be dissent regarding High-NA use, especially within the lithography departments. The depth of…

— Fred Chen on November 1, 2026
TSMC’s Patent and the Harsh Realities of 3D DRAM Competition
If AI needs force memory to be made on the same chip as the AI logic processor, since HBM is…

— Fred Chen on October 30, 2026
Why America’s Semiconductor Manufacturing Capacity Matters
an IP without the ability to manfacture is meaningless. intels struggle are not IDM Struggle but self inflicting injuries aka…

— siliconbruh999 on October 28, 2026
ChipAgent Raises $134Million and Why it Matters
<> Now we can add Rambus to that list - both a customer and an equity investor: https://www.rambus.com/rambus-and-chipagents-collaborate-to-accelerate-chip-design-with-agentic-ai/

— DougDD on October 25, 2026
Why America’s Semiconductor Manufacturing Capacity Matters
The superpower that the US has as an innovator is the ability to bring capital and brilliant people together, and…

— Mark M Stark on October 25, 2026

electronica 2026

SEMICON Europa 2026

SC26

Hardwear.io Security Trainings and Conference NL 2026

China OIP Ecosystem Forum

Podcast EP378: An Overview of the 2026 Wilson Research Group Functional Verification Study with Harry Foster

CEO Interview with Sergiy Nesterenko of Quilter on AI PCB Layout

CTO Interview With Juan Rey, senior VP and general manager of Calibre and CTO of Siemens EDA

CTO Interview Kevin Robinson, VP of Operations, yieldHUB

CXO Interview with Solaiman Rahim of ChipAgents

Three-Dimensional Chess Anyone? The Challenges of Power Integrity for Multi-Die Designs

Golden Testcases You Can Check With a Calculator

Curvilinear OPC and next-gen photomask optimization

ChipNexus Brings Agentic AI into Established Analog Design Flows

CEO Interview with Jun Yuan of Arcas-Tech

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Recent Article Comments

The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival

The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival

Intel’s Tiny Bridges Could Lead to Very Big Paychecks

High-NA’s Obituary Was Premature

TSMC’s Patent and the Harsh Realities of 3D DRAM Competition

Why America’s Semiconductor Manufacturing Capacity Matters

ChipAgent Raises $134Million and Why it Matters

Why America’s Semiconductor Manufacturing Capacity Matters