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Electronic Design Automation
There is an interesting article by Kexun ZHang of ChipAgents on their blogsite. This is a company to watch, absolutely. Here is my take on it:
Software engineering has already demonstrated the trajectory of agentic AI. Coding tools progressed from autocomplete to systems that interpret requests, inspect repositories, modify… Read More
AttoTude has expanded its use of Keysight Technologies’ Advanced Design System (ADS) to support an integrated-circuit design flow spanning signaling frequencies from 100 GHz to 3 THz. The company reports that the resulting workflow has reduced IC development cycles by more than 50%, enabling projects to move from concept to… Read More
Agentrys recently launched a new category of design technology, Agentic Design Automation (ADA). The approach promises to revolutionize AI deployment for chip design with technology that facilitates the building of targeted agentic design flows that get better with every run. There is a lot of information available on the … Read More
Agentic AI was everywhere at DAC 2026. Various focus areas were presented that covered many parts of the chip design flow. Verification and debug were a popular topic since so much time is spent there. Analog design is another pressure point. Every chip design has analog content. While the size of the analog blocks may not be huge,… Read More
Frontier models (Claude, etc.) are very powerful but becoming expensive for high token counts. Methods to exploit a mix of models, including local open-weight models, are attracting attention. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer… Read More
Agentic artificial intelligence is likely to give the open-source electronic design automation market a meaningful boost. Its biggest contribution will not be the immediate replacement of established commercial platforms from Cadence, Synopsys, or Siemens. Instead, agentic AI can make open-source tools easier to use, … Read More
Why Advanced-Node Clock Networks Need More Than Timing Closure
Timing closure has been one of the semiconductor industry’s most reliable measures of design readiness for decades. Static timing analysis (STA) is a critical enabler for this process. It allows analysis of enormous designs across millions of paths, multiple… Read More
During my time at DAC 2026 I felt like I was attending two events. One was the traditional DAC where approaches to designing complex chips using the best tools and methodologies were the focus. There was another focus for the conference. This one was like the traditional DAC with an important difference. Here, the discussion centered… Read More
The reported move of Amit Gupta, Jeff Dyck, and Ryan Silk from Siemens EDA to Synopsys matters because this is more than a routine transfer of experienced executives and engineers. Together, the three represent a concentrated body of expertise in applying artificial intelligence to semiconductor design—one of the most strategically… Read More
In advanced packaging, warpage is rarely a modeling problem. It is a timing problem.
JOHN BRUGGEMAN
By the time many advanced packages undergo high-fidelity thermo-mechanical analysis, a long chain of decisions has already been made. Stackup. Materials. Die placement. Package architecture. Each decision constrains the … Read More
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Intel’s 14A Is Winning the Race Against Defects