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Electronic Design Automation
Dr. Raj Gautam Dutta is the Co-Founder and Chief Executive Officer of Silicon Assurance, where he defines the company’s strategic direction and leads its technology and product vision. He is responsible for driving the development of differentiated hardware security solutions, executing growth and partnership strategies,… Read More
Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More
Clock power is rarely the issue teams expect to limit advanced-node designs. Yet in many chips today, over-driven clock networks quietly consume disproportionate power, reduce thermal headroom, and can constrain achievable frequency. And all while passing traditional sign-off checks and often remaining locked in through… Read More
Physical AI is an emerging hot trend, popularly associated with robotics though it has much wider scope than compute systems interacting with the physical world. For any domain in which analysis rests on differential equations (foundational in physics), the transformer-based systems behind LLMs are not the best fit for machine… Read More
Tell us a little bit about yourself and your company.
My name’s Abhijeet Chakraborty and I’m Vice President of Engineering at Synopsys. I led the development of Synopsys Design Compiler-NXT, the industry’s leading synthesis product, and now oversee the company’s multi-die and 3DIC product portfolio. Throughout my career,… Read More
I first learned about ATPG – Automatic Test Program Generation in the 1980s at Silicon Compilers, then continued in the 90s at Viewlogic with the Sunrise tools, so it was illuminating to get an update from Synopsys on their ATPG technology by attending a webinar. Synopsys over the years has developed a family of test tools, shown … Read More
The Design Automation Chips to Systems Conference is the preeminent international event for professionals involved in electronic design, system architecture, and EDA. Formerly known simply as the Design Automation Conference or DAC has evolved over more than six decades into a forward-looking forum that spans the entire… Read More
Clock jitter rarely fails in obvious ways. In advanced-node designs, its impact is often indirect, emerging through subtle timing uncertainty, interaction with power delivery noise, and compounding effects across large clock networks. These behaviors can quietly erode margin and predictability, even when conventional… Read More
Synopsys and AMD were recently selected by the World Economic Forum for inclusion in the WEF’s MINDS (Meaningful, Intelligent, Novel, Deployable Solutions) AI program, recognizing their leadership and real-world impact in applying generative and agentic AI to semiconductor design and engineering. This distinction places… Read More
As usual in January we start with a look back at the papers we reviewed last year. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.
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