Dr. Solaiman Rahim is a multidisciplinary technology executive with over 25 years of experience driving innovation in the chip automation space at the intersection of systems, semiconductors, high-performance computing, and AI. As Chief Product Officer at ChipAgents, he leads the scaling of the Agentic and Native AI platform… Read More
Electronic Design Automation
Three-Dimensional Chess Anyone? The Challenges of Power Integrity for Multi-Die Designs
Power integrity has been a substantial design challenge for a long time. In the multi-die era, the problems associated with EMIR analysis must now move beyond the chip to consider interactions across the entire stack. The effects to be analyzed span a multi-dimensional, multi-material space. The graphic at the top of this post… Read More
Golden Testcases You Can Check With a Calculator
Two timing tools that agree can still both be wrong. A small testcase where you can re-derive every printed digit by hand shows that the engine is correct, and when it isn’t, it shows which term is wrong.
By Dr. Sameer Pawanekar, Founder & CEO, Ramtera Inc.
The problem: agreement is not correctness
New static timing engines, and… Read More
Curvilinear OPC and next-gen photomask optimization
A vector-based approach for semiconductor manufacturing
By Sagar Saxena is a Senior Product Engineer at Siemens EDA
Curvilinear OPC transforms advanced semiconductor manufacturing
Modern semiconductor manufacturing is experiencing a fundamental shift in the way photomasks are created and optimized. As the industry pushes… Read More
CEO Interview with Jun Yuan of Arcas-Tech
JUN YUAN BIO
◆Engineer for chip design, simulation, and P&R at AMD; Senior Engineer for chip verification (emulation, equivalence checking, formal verification) at Motorola since 1992.
◆Held R&D and technical management roles in formal verification EDA at Verplex, Jasper, and Cadence since 2003.
◆Founded Arcas-tech… Read More
ChipNexus Brings Agentic AI into Established Analog Design Flows
ChipNexus has introduced its NEX Analog Agent, bringing conversational automation to analog engineering workflows built around Cadence Virtuoso, Spectre simulation and Siemens Calibre physical verification. Available now, the software operates with customers’ installed tools, licenses and process design kits, giving… Read More
Interview with David Tester VP of Engineering Mach42
David Tester is the VP of Engineering at Mach42, with 30 years of experience in semiconductor development, engineering leadership, and business growth. As Chief Engineer at EnSilica, he helped transform the company from a design consultancy into a publicly listed fabless semiconductor business, scaling the organisation … Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity
By Defacto Staff
Today’s chips are no longer just processors, they are entire systems. A System-on-Chip (SoC) brings together CPU clusters, accelerators, memories, interconnects and dozens of peripherals, often coming from many different teams and vendors. With AI, high-performance computing and IoT driving demand for … Read More
Reimagining 3D IC Design: From Architecture to Signoff
By Keith Felton, Andras Vass-Varnai and Todd Burkholder, Siemens EDA
The semiconductor industry is undergoing a fundamental transformation. Heterogeneous integration, the practice of combining multiple chiplets and specialized components into a single advanced packaging platform, has emerged as a powerful alternative… Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival