You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today!
WP_Term Object
(
[term_id] => 157
[name] => EDA
[slug] => eda
[term_group] => 0
[term_taxonomy_id] => 157
[taxonomy] => category
[description] => Electronic Design Automation
[parent] => 0
[count] => 4095
[filter] => raw
[cat_ID] => 157
[category_count] => 4095
[category_description] => Electronic Design Automation
[cat_name] => EDA
[category_nicename] => eda
[category_parent] => 0
[is_post] =>
)
Greg Law is a C++ debugging expert, well-known conference speaker, and the founder of Undo. Greg has over 20 years’ experience in the software industry working for the pioneering British computer firm Acorn, as well as NexWave and Solarflare.
Determined to build a tool to ease the pain of debugging complex software, he started… Read More
We have been hearing so much lately about the power of AI and the potential of technologies like agentic AI to address the productivity gap and complexities of semiconductor designs of today and tomorrow. Currently, however, the semiconductor industry has been slow to adopt generative and agentic AI for RTL design code. There… Read More
We have talked about metamorphic testing before. Here is a clever application to testing an AMS subsystem. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.… Read More
In part one of this webinar series, Keysight and Modelithics looked at the use of 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation of high-frequency RF board designs. Part two continues the exploration of RF board design flows for simulating active circuits on boards, again… Read More
For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal… Read More
How much perfectly good silicon is being discarded in the quest for reliability? During high-volume chip manufacturing, aggressive testing with strict thresholds may ensure quality but reduces yield, discarding marginal chips that could function flawlessly. On the other hand, prioritizing yield risks allowing defective… Read More
Automotive electronics is a fast-moving space, especially around sensing and distilling intelligence from that sensing. This serves three main pillars: autonomy, electrification and advances in the car cockpit. Autonomy at multiple levels remains an important goal and continues to advance, technically and geographically.… Read More
While Cadence and Synopsys were sharing a lot of detail over the past few years about what they were doing in AI, Siemens EDA seemed content to offer a very general picture about their intentions without getting into a lot of detail. At DVCon 2025 they finally pulled back the curtain. Why wait until now to announce?
Darron May (Director… Read More
Custom and analog/mixed-signal IC designs have some unique IP and symmetry checking requirements for physical design. Waiting until the end of the IC layout process to verify IP instances for correctness or proper symmetry will cause project delays, so an approach to perform earlier physical verification makes more sense. … Read More
The tech world is sprinting toward a future where your fridge orders groceries, your car avoids traffic before you hit it, and security cameras don’t just watch—they understand. But behind these innovations lies a messy truth: building the brains for these smart systems is complicated.
Fresh off the 2024 Arm Tech Symposia… Read More
Rethinking Multipatterning for 2nm Node