800x100 Webinar (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4056
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4056
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Accelerating FPGA-Based SoC Prototyping

Accelerating FPGA-Based SoC Prototyping
by Kalar Rajendiran on 01-16-2025 at 10:00 am

S2C Image for SoC Prototyping Blog

FPGA-based prototyping offers advantages such as high-speed operation, real-world environment testing, and parallel execution that cannot be matched by software simulations alone. It enables developers to validate their designs and initiate software development long before the final silicon is ready. At the same time,… Read More


Chiplet integration solutions from Keysight at Chiplet Summit

Chiplet integration solutions from Keysight at Chiplet Summit
by Don Dingee on 01-15-2025 at 10:00 am

signal integrity of electrical layer in UCIe

Chiplets continue gaining momentum, fueled in large part by applications for AI and 5G/6G RFICs. Keysight has a strong presence at this year’s Chiplet Summit in Santa Clara, which includes Simon Rance in a super panel discussing “Chiplets: The Key to Solving the AI Energy Gap” and Nilesh Kamdar with a keynote… Read More


A Deep Dive into SoC Performance Analysis: What, Why, and How

A Deep Dive into SoC Performance Analysis: What, Why, and How
by Lauro Rizzatti on 01-15-2025 at 6:00 am

A Deep Dive into SoC Performance Analysis Part 1 Figure 2

Part 1 of 2 – Essential Performance Metrics to Validate SoC Performance Analysis

Part 1 provides an overview of the key performance metrics across three foundational blocks of System-on-Chip (SoC) designs that are vital for success in the rapidly evolving semiconductor industry and presents a holistic approach to optimizeRead More


2025 Outlook with Dr. Chouki Aktouf of Innova

2025 Outlook with Dr. Chouki Aktouf of Innova
by Daniel Nenni on 01-14-2025 at 10:00 am

Picture Chouki

Chouki Aktouf is Founder & CEO of Defacto Technologies and Co-Founder of Innova Advanced Technologies.  Prior to founding Defacto in 2003, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble – France and leader of a dependability research group. He holds a PhD in Electric Engineering from… Read More


WEBINAR: Reconcile Design Cost Reduction & Eco-design Criteria for Complex Chip Design Projects

WEBINAR: Reconcile Design Cost Reduction & Eco-design Criteria for Complex Chip Design Projects
by Daniel Nenni on 01-14-2025 at 6:00 am

flow innova2

As chip design complexity keeps increasing, the challenge of managing costs becomes a pressing concern for companies of all sizes. Efficient resource management is emerging as a critical lever for controlling design expenses and ensuring project success.

The chip design market increasingly demands automated solutions for… Read More


Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques

Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques
by Kalar Rajendiran on 01-13-2025 at 10:00 am

CMA:SPDM Flow for Establishing a Secure Connection

In today’s digital landscape, data security has become an indispensable feature for any data transfer protocol, including Peripheral Component Interconnect Express (PCIe). With the rising frequency and sophistication of digital attacks, ensuring data integrity, confidentiality, and authenticity during PCIe transport… Read More


ML and Multiphysics Corral 3D and HBM

ML and Multiphysics Corral 3D and HBM
by Bernard Murphy on 01-07-2025 at 6:00 am

multidie and HBM stacks min

3D design with high-bandwidth memory stacks (HBM) has become essential for leading edge semiconductor systems in multiple applications. Hyperscalers depend on large AI accelerator cores supported by 100GB or more of in-package HBM to handle trillion parameter AI models. Autonomous Drive (AD) vehicles may handle smaller … Read More


Accelerating Automotive SoC Design with Chiplets

Accelerating Automotive SoC Design with Chiplets
by Kalar Rajendiran on 01-02-2025 at 10:00 am

System Chiplet

The automotive industry is evolving rapidly with the increasing demand for intelligent, connected, and autonomous vehicles. Central to this transformation are System-on-Chip (SoC) designs, which integrate multiple processing units into a single chip for managing everything from safety systems to in-car entertainment.… Read More


Accelerating Simulation. Innovation in Verification

Accelerating Simulation. Innovation in Verification
by Bernard Murphy on 12-30-2024 at 6:00 am

Innovation New

Following a similar topic we covered early last year, here we look at updated research to accelerating RTL simulation through domain-specific hardware. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our … Read More


Ultra Ethernet and UALink IP solutions scale AI clusters

Ultra Ethernet and UALink IP solutions scale AI clusters
by Don Dingee on 12-19-2024 at 6:00 am

UALink and Ultra Ethernet roles in AI infrastructure clusters

AI infrastructure requirements are booming. Larger AI models carry hefty training loads and inference latency requirements, driving an urgent need to scale AI acceleration clusters in data centers. Advanced GPUs and NPUs offer solutions for the computational load. However, insufficient bandwidth or latency between servers… Read More