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Rethinking ECAD IT Infrastructure: From Fragmentation to an Engineering Platform

Rethinking ECAD IT Infrastructure: From Fragmentation to an Engineering Platform
by Kalar Rajendiran on 05-04-2026 at 6:00 am

The semiconductor industry is entering a new phase of complexity. Advanced nodes, heterogeneous integration, and AI-driven design workflows are placing unprecedented demands on engineering teams. While much of the focus remains on tools and methodologies, an equally critical constraint is emerging beneath the surface:… Read More


Bronco AI Webinar: Full-Chip SoC Debug in 15 Minutes

Bronco AI Webinar: Full-Chip SoC Debug in 15 Minutes
by Daniel Nenni on 05-01-2026 at 10:00 am

BroncoBlogPostDetective

A single bug on a full-chip SoC can pull engineers off roadmap work for days or even weeks. It involves massive waveforms, thousands of files of RTL and UVM, and dense specs that aren’t always perfect. Finding these bugs have always been a matter of engineer-hours and how well knowledge diffuses through the organization.

Bronco … Read More


IPLM: Future Forward Webinar May 19th

IPLM: Future Forward Webinar May 19th
by Daniel Nenni on 05-01-2026 at 8:00 am

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Step into the future of innovation with the IPLM: Future Forward Webinar—a dynamic, insight-packed event designed for professionals who are ready to rethink how ideas evolve into impact. In a rapidly shifting digital landscape, staying ahead means more than keeping up—it means anticipating change, embracing transformation,… Read More


Solving the EDA tool fragmentation crisis

Solving the EDA tool fragmentation crisis
by Admin on 04-30-2026 at 10:00 am

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By Samar Abd El-Hady and Wael ElManhawy

Design teams today face an uncomfortable truth: the specialized tools they need to verify modern ICs can’t reliably share the same design data. As geometries shrink below five nanometers and designs incorporate billions of transistors across multiple dies, no single Electronic… Read More


Complex PCB signoff challenges

Complex PCB signoff challenges
by Daniel Payne on 04-28-2026 at 10:00 am

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Many complex PCB designs have high data-rate signals like USB, PCIe, DDR and HDMI which call for more thorough verification methods to ensure compliance plus mitigate any signal integrity, power integrity and EMI/EMC issues. Siemens has a methodology that uses automated rule-based electrical verification with an EDA tool,… Read More


UX in Agentic Systems. Innovation in Verification

UX in Agentic Systems. Innovation in Verification
by Bernard Murphy on 04-28-2026 at 6:00 am

Innovation New

A switch this month to principles behind building effective agentic systems, going beyond simply a new way to stitch together tools, agents and orchestration, to deeper consideration of user experience and how we most effectively blend agentic with human-in-the-loop. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano… Read More


Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions

Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions
by Kalar Rajendiran on 04-23-2026 at 10:00 am

Looking Forward Slide

 

Semiconductor manufacturing has become one of the most data-intensive industrial environments in the world, and AI is rapidly becoming central to how fabs operate and optimize. Yet, rather than converging on a single model for AI adoption, the industry is evolving along two distinct paths. One centered on platform-scale… Read More


How to Overcome the Advanced Node Physical Verification Bottleneck

How to Overcome the Advanced Node Physical Verification Bottleneck
by Mike Gianfagna on 04-22-2026 at 6:00 am

How to Overcome the Advanced Node Physical Verification Bottleneck

It is well-known that advanced semiconductor process technology presents substantial challenges across the full design flow and global supply chain. In this piece, we will focus on a particularly difficult problem – physical verification. This design step is the final gate to manufacturing. Producing a final tape‑out GDS … Read More


WEBINAR: Intrinsic Techniques in RF Power Amplifier Design

WEBINAR: Intrinsic Techniques in RF Power Amplifier Design
by Don Dingee on 04-20-2026 at 10:00 am

Intrinsic node overview

Load-pull power amplifier (PA) design techniques determine the optimal impedances at the power transistor’s extrinsic reference plane, which is the physically accessible boundary for measurement or simulation. This reference plane can be the package transistor leads, die bond pads, or IC chip terminals. It includes… Read More


Podcast EP342: The Evolution and Impact of Physical AI with Hezi Saar

Podcast EP342: The Evolution and Impact of Physical AI with Hezi Saar
by Daniel Nenni on 04-17-2026 at 6:00 am

Daniel is joined by Hezi Saar, Executive Director of Product Marketing at Synopsys, Hezi is responsible for the mobile, automotive, and consumer IP product lines. He brings more than 20 years of experience in the semiconductor and embedded systems industries.

Dan explores the growing field of physical AI with Hezi, who explains… Read More