CNM banner
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4536
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4536
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Formal Acceleration on FPGA. Innovation in Verification

Formal Acceleration on FPGA. Innovation in Verification
by Bernard Murphy on 07-30-2026 at 6:00 am

Innovation New

Extending hardware acceleration to formal verification is a powerful idea to extend hardware acceleration to a verification domain that has not got much attention for acceleration. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More


ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation

ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation
by Daniel Nenni on 07-29-2026 at 10:00 am

S2C FPGA Prototyping

For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More


How early symmetry validation eliminates costly late-stage respins

How early symmetry validation eliminates costly late-stage respins
by Admin on 07-27-2026 at 2:00 pm

article fig1 shift left

By Mauli Shah, Product Engineer, Siemens

Analog and mixed-signal design teams face a persistent challenge that directly impacts tape-out schedules and project predictability: symmetry violations discovered at signoff trigger expensive respins, delay schedules and create unpredictable iteration cycles. Despite symmetry… Read More


Rethinking Formal Verification in the AI Era

Rethinking Formal Verification in the AI Era
by Admin on 07-27-2026 at 10:00 am

AI driven formal verification

By Kanav Arora, ML Researcher at ChipAgents

Most hardware teams already understand why formal verification matters. It can expose corner cases that simulation may never reach and establish critical behaviors across the modeled state space.

The unresolved question is not whether formal works. It is why formal remains a specialist… Read More


CEO Interview with Ann Wu and Akash Levy of Silimate

CEO Interview with Ann Wu and Akash Levy of Silimate
by Daniel Nenni on 07-27-2026 at 8:00 am

ann headshot 2024 yellow

Ann Wu is Co-founder & CEO of Silimate. Before Silimate, Ann designed several generations of custom silicon at Apple, helped manage inference ASIC programs at Meta, and led product strategy and execution at Celestial AI. Ann has a M.S. in Electrical Engineering from Stanford University and a B.S. in Electrical Engineering… Read More


From Process Learning to Production Control: Characterization for the Era of Heterogeneous Systems

From Process Learning to Production Control: Characterization for the Era of Heterogeneous Systems
by Kalar Rajendiran on 07-27-2026 at 6:00 am

Chiplets Have Changed the Test Paradigm

Every generation of semiconductor innovation has relied on one fundamental principle: before a technology can be manufactured at scale, it must first be understood. That understanding comes through characterization.

For decades, characterization enabled process learning. It helped engineers understand transistor behavior,… Read More


CEO Interview with Ohad Agami of Hiveware

CEO Interview with Ohad Agami of Hiveware
by Daniel Nenni on 07-26-2026 at 2:00 pm

ohad3

Ohad Agami is the co-founder and CEO of Hiveware, a semiconductor verification company he started in Tel Aviv in 2023 with CTO Yaniv Pascal. He has a systems-focused engineering background with deep experience in semiconductor architectures and complex verification flows, built at the AI chip company Hailo and earlier in Israel’s… Read More


Agentrys Designs a Real Chip with its Multi-Agent Workforce

Agentrys Designs a Real Chip with its Multi-Agent Workforce
by Mike Gianfagna on 07-23-2026 at 2:00 pm

Agentrys Designs a Real Chip with its Multi Agent Workforce

The face of EDA is changing. For forty years, this industry has focused on optimizing algorithms for design, verification and implementation of chips. That work has delivered some ground-breaking innovations. Logic synthesis is a good example. There are so many more. Thanks to the innovations commonly referred to as FrontierRead More


Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?

Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
by Mike Gianfagna on 07-23-2026 at 10:00 am

Panel

This year, DAC will be buzzing about AI from every direction. The debate of build vs. buy will also be a popular topic. And the debate of who owns the intellectual property embodied in chip designs and how to control it will also get a significant amount of airtime. These are all interesting and compelling discussion points. It turns… Read More


BRONCO AI: WIN THE RACE TO TAPE-OUT | BOOTH 935

BRONCO AI: WIN THE RACE TO TAPE-OUT | BOOTH 935
by Daniel Nenni on 07-23-2026 at 8:00 am

Bronco Dac26 Semiwiki Banner

Bronco AI builds AI agents for chip design and verification. Our goal is to get teams from spec to RTL-freeze as fast as possible by surfacing the nastiest bugs sooner and fixing them faster.

Our agents work the way strong engineers do: they read the spec, form hypotheses, run experiments, and chase a problem until it is root-caused,… Read More