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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4580
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4580
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Podcast EP365: How Agentrys is Revolutionizing Chip Design with Mark Ren

Podcast EP365: How Agentrys is Revolutionizing Chip Design with Mark Ren
by Daniel Nenni on 09-11-2026 at 10:00 am
Categories: Agentrys, EDA

Daniel is joined by Mark Ren, founder and CEO of Agentrys. Mark has 26 years of EDA and AI R&D experience spanning IBM Research and NVIDIA Research, driving design automation innovations that power modern chip design. He received the IBM Corporate Award for contributions to the design closure for high-performance microprocessors.… Read More

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Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success

Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success
by Mike Gianfagna on 09-10-2026 at 2:00 pm
Categories: AI, EDA, Events, Tuple Technologies

Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success

Studies have shown that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration. This work remains largely manual today or is delegated to general-purpose LLMs that can produce incorrect assertions more than 30% of the time. Avestra attacks this problem with agentic AI … Read More

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PDF Solutions CONNECT 2026: Where Semiconductor Data Meets AI

PDF Solutions CONNECT 2026: Where Semiconductor Data Meets AI
by Daniel Nenni on 09-10-2026 at 10:00 am
Categories: EDA, Events, PDF Solutions

CONNECT 400x400

The semiconductor industry is entering a period in which manufacturing leadership will depend not simply on producing more data, but on turning that data into timely, trustworthy decisions. PDF Solutions CONNECT 2026 is designed around this challenge. Taking place October 15–16 at the Westin St. Francis in San Francisco, the… Read More

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Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI
by Mike Gianfagna on 09-10-2026 at 6:00 am
Categories: AI, ChipAgents AI, EDA, Events

Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

We all know timing closure is one of the most challenging processes in chip design. Extracting actionable insight from massive timing reports, tracing violations back to RTL, and selecting the right fix across complex PPA tradeoffs all require deep expertise. And every change can trigger hours or days of tool runs and cross-team… Read More

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Keysight EDA update at DAC 2026

Keysight EDA update at DAC 2026
by Daniel Payne on 09-09-2026 at 10:00 am
Categories: EDA, Keysight EDA

keysight dac2026

On the last day of #DAC2026 I stopped by the Keysight booth to chat with Nilesh Kamdar, GM of EDA Business to get an update. He has spent 27 years in the industry, and this made 25 DAC trips for him. For Keysight the application areas of focus are serving designers of high frequency and high-speed digital, RF, and mm/uwave designs. An … Read More

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AI Memory Gap at DAC 2026

AI Memory Gap at DAC 2026
by Daniel Payne on 09-07-2026 at 10:00 am
Categories: EDA, Synopsys

AI memory gap

On Tuesday at #DAC2026 I attended the exhibitor presentation, Synopsys: How Silicon Startups are Addressing the AI Memory Gap. Vikram Bhatia from Synopsys introduced the two presentations from Wenbo Yin, SVP of IC Design at TetraMem and R. Scott Hills, VP of Business Development at ANAFLASH. Datacenters consume large amounts… Read More

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When Design Gets Faster, the Bottleneck Moves Through the Physical Stack

When Design Gets Faster, the Bottleneck Moves Through the Physical Stack
by Moh Kolb on 09-07-2026 at 6:00 am
Categories: EDA, Semiconductor

Desing fast Bott through physicalstack

AI can compress the path to tape-out. The next challenge is compressing physical realization.

Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.

AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More

Podcast EP364: The Broad Impact of Advanced Mask Solutions, Today and Tomorrow with Dr. Germain Fenger

Podcast EP364: The Broad Impact of Advanced Mask Solutions, Today and Tomorrow with Dr. Germain Fenger
by Daniel Nenni on 09-04-2026 at 10:00 am
Categories: EDA, Synopsys

Daniel is joined by Dr. Germain Fenger, Senior Director of Product Management at Synopsys where he leads advanced mask solutions and computational lithography technologies. With a background spanning semiconductor manufacturing, lithography research, engineering, and product leadership, Germain has held roles at imec,… Read More

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The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response

The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response
by Kalar Rajendiran on 09-04-2026 at 6:00 am
Categories: AI, Arm, IP, IPnest, RISC-V, Semiconductor, Semiconductor Intelligence, Semiconductor Services, SiFive, Synopsys
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2025 Design IP Sub Categories Market Share Pie Chart

While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More

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Technical Case Study: MicroLED Yield Management with Plessey and yieldWerx

Technical Case Study: MicroLED Yield Management with Plessey and yieldWerx
by Daniel Nenni on 09-03-2026 at 2:00 pm
Categories: EDA, yieldWerx

Technical Case Study MicroLED Yield Management at Plessey

Plessey Semiconductors manufactures monolithic MicroLED displays for near-eye augmented-reality systems, where pixel pitch, brightness, uniformity, and defect density directly determine usable yield. Its process integrates device design, epitaxy, wafer fabrication, bonding, and production in one facility. The displays… Read More