2
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4554
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4554
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

SEMICON West 2026: AI Made the Steps Faster. The Time Between Them Is Next.

SEMICON West 2026: AI Made the Steps Faster. The Time Between Them Is Next.
by Joel Jorgensen on 10-29-2026 at 10:00 am

SemiWiki SEMICON West Inline Time Between

The semiconductor industry crossed $1 trillion in annual revenue this year, almost four years ahead of earlier projections. SEMI President and CEO Ajit Manocha opened the CEO Summit at SEMICON West with a chart that told the story. A year ago, the forecast for 2030 was $1 trillion. Now it is $2 trillion, with $3 trillion possible … Read More


PDF Solutions CONNECT 2026 Trip Report

PDF Solutions CONNECT 2026 Trip Report
by Lauro Rizzatti on 10-29-2026 at 8:00 am

PDF Solutions CONNECT 2026 trip report

On October 15–16, at the tail end of SEMICON West 2026, PDF Solutions held its 2026 CONNECT Conference at the Westin St. Francis in San Francisco.

PDF Solutions Vitals

Santa Clara–based PDF Solutions is a semiconductor data, analytics, and connectivity company, founded in 1991. Today, its business rests on three pillars, all … Read More


ML-Based Power Models for CPUs. Innovation in Verification

ML-Based Power Models for CPUs. Innovation in Verification
by Bernard Murphy on 10-29-2026 at 6:00 am

Innovation New

An effective learned power model for a CPU could be a significant advantage in early estimation of power performance against realistic workloads in complex architectures. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More


ChipAgents Expands AI Across Chip Design. The Test Is Faster, Verified Results

ChipAgents Expands AI Across Chip Design. The Test Is Faster, Verified Results
by Daniel Nenni on 10-27-2026 at 10:00 am

chipagents announcement

ChipAgents is expanding its agentic AI platform across digital and analog semiconductor engineering, aiming to connect fragmented design workflows through a common system that can plan tasks, operate engineering tools and evaluate results.

The Santa Clara company says its IC-Star engine combines organizational design … Read More


Why Synopsys’ Role in AMD’s Instinct MI455X Matters for AI Infrastructure

Why Synopsys’ Role in AMD’s Instinct MI455X Matters for AI Infrastructure
by Daniel Nenni on 10-27-2026 at 8:00 am

Conceptual Multi Die AI GPU Design

Synopsys’ collaboration with AMD on the Instinct MI455X GPU highlights a shift in how advanced AI processors are developed. Increasing performance depends on coordinating compute dies, memory interfaces, packaging, power delivery, and software. According to Synopsys’ announcement, AMD used its design, verification, … Read More


S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

S2C Targets Faster RISC-V Bring-Up With Prototyping and AI
by Daniel Nenni on 10-27-2026 at 6:00 am

S2C advances RISC V FPGA development

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V systems on FPGA hardware,… Read More


WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro

WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro
by Daniel Nenni on 10-23-2026 at 8:00 am

Smarter EDA Queues with Stratos AI

Expensive EDA licenses should keep chip design moving. Yet when license activity and job queues live in separate systems, teams can struggle to understand why work is waiting, which tools are underused, and whether additional spending will solve the problem. Idle seats, checkout failures, and stalled jobs can consume budgets… Read More


Beyond the Post-Mortem: How yieldHUB Live Turns the Test Floor Into an Open Window

Beyond the Post-Mortem: How yieldHUB Live Turns the Test Floor Into an Open Window
by Lauro Rizzatti on 10-21-2026 at 10:00 am

Live visibility on the semiconductor test floor (1)

At SEMICON West 2026 I sat down with John O’Donnell, founder and CEO, and Gillian O’Donnell, Director of Growth, to talk about how yieldHUB Live is transforming the semiconductor test floor from a blind spot into a real-time command center.

For decades, semiconductor test floors have operated as high-stakes black… Read More


Who Gets to Move the Recipe? How Autonomous Agents Earn Decision Authority in the Fab

Who Gets to Move the Recipe? How Autonomous Agents Earn Decision Authority in the Fab
by Admin on 10-20-2026 at 8:00 am

featured who gets to move the recipe

by Ajay Kumar Govindaram

There’s a question I’ve started asking at every agentic AI demo I sit through, and it has a clean answer in every fab on earth: who is allowed to change the recipe? In a semiconductor factory, that was settled decades ago. A person doesn’t touch a production recipe because they feel confident.… Read More


Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering

Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering
by Mike Gianfagna on 10-19-2026 at 10:00 am

Agentic Loops, Autonomous Chip Design

At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from… Read More