Cisco’s relentless push toward higher-performance networking silicon has placed extraordinary demands on its ASIC design methodology. As transistor densities continue to rise across advanced SoCs, traditional design-time guardbands are no longer sufficient to ensure long-term reliability, consistent performance,
Electronic Design Automation
Simulating Quantum Computers. Innovation in Verification
Quantum algorithms must be simulated on classical computers to validate correct behavior, but this looks very different from classical logic simulation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our… Read More
Assertion-First Hardware Design and Formal Verification Services
Generative AI has transformed software development, enabling entire applications to be built in minutes. But despite similar progress in AI-generated RTL, hardware verification remains a major bottleneck. RTL can be produced quickly, yet proving its correctness is extraordinarily difficult. This has revived a long-standing… Read More
PDF Solutions’ AI-Driven Collaboration & Smarter Decisions
When most people hear the term PDF, they immediately think of a PDF file, a universal, platform-independent way to share electronic documents.
There is, however, another PDF that many outside the semiconductor industry may not be familiar with. And this PDF actually predates the PDF file format. It is short for PDF Solutions, … Read More
Bringing Low-Frequency Noise into Focus
Key takeaways
- The challenge of acquiring high-quality, reproducible noise data becomes achievable with Primarius’ wafer-level low-frequency noise characterization solution, which is essential for advanced nodes.
- The Primarius 981X family raises the bar for low-frequency noise measurement metrology with its unique
Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson
Daniel is joined by John Ferguson, senior director of product management for the Calibre products in the 3DIC space at Siemens EDA. He manages the vision and product offerings in the Calibre domain for 3DIC design solutions.
Dan explores the challenges of 3DIC and chiplet-based design with John, who describes the broad range of… Read More
How vHelm Delivers an Optimized Clock Network
In a prior post, I discussed how the clock is no longer just another signal at advanced nodes. Indeed, it is the most critical network on the chip. An optimized clock network can be the margin of victory for your next design. But extracting these benefits is challenging. The clock network is quite sensitive, and optimization can come… Read More
Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies
Our good friend Scotten Jones wrote a paper on a product that has been in joint development with Synopsys and is now available. Scott is currently President Semiconductor Manufacturing Economics and Senior Fellow at TechInsights. Scott and I have discussed this product many times and I feel it is ground breaking technology for… Read More
3D ESD verification: Tackling new challenges in advanced IC design
By Dina Medhat
Three key takeaways
- 3D ICs require fundamentally new ESD verification strategies. Traditional 2D approaches cannot address the complexity and unique connections in stacked-die architectures.
- Classifying external and internal IOs is essential for robust and cost-efficient ESD protection. Proper differentiation
Reimagining Architectural Exploration in the Age of AI
This is not about architecting a full SoC from scratch. You already have a competitive platform, now you want to add some kind of accelerator, maybe video, audio, ML, and need to explore architectural options for how accelerator and software should be partitioned, and to optimize PPA. Now we have AI to help us optimize you’d like … Read More


Quantum Computing Technologies and Challenges