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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4488
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4488
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Synopsys Unifies Electrical, Thermal, Mechanical, and Optical Analysis with Multiphysics Fusion Solutions

Synopsys Unifies Electrical, Thermal, Mechanical, and Optical Analysis with Multiphysics Fusion Solutions
by Daniel Nenni on 06-17-2026 at 2:00 pm

Synopsys Announces Availability of the First Wave of Multiphysics Fusion Solutions

Synopsys has announced the availability of the first wave of its Multiphysics Fusion Solutions, extending its vision of a unified engineering environment that connects EDA, semiconductor physics, system simulation, and artificial intelligence-driven optimization. The announcement addresses one of the most significant… Read More


PowerArtist RTL Power Estimation Folds into Keysight

PowerArtist RTL Power Estimation Folds into Keysight
by Bernard Murphy on 06-17-2026 at 6:00 am

PowerArtist exploring and fixing hotspots in a GPU

Back in the late 1990s, Sente launched a product called WattWatcher to estimate power from design RTL and simulation activity. This was revolutionary for its time since alternatives, while very accurate, only offered power analysis at the gate level. Gate-level analysis is great for fine-tuning power but is unhelpful for achieving… Read More


GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck

GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck
by Admin on 06-16-2026 at 10:00 am

fig1 gpu opc challenge

As semiconductor manufacturing pushes toward advanced nodes with tighter feature sizes, the optical proximity correction (OPC) workflow is adopting curvilinear masks to achieve the larger process windows that traditional Manhattan geometries cannot deliver.

Traditional Manhattan masks constrain shapes to vertical … Read More


Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner

Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner
by Kalar Rajendiran on 06-15-2026 at 6:00 am

ESDA Panel Session June 10, 2026 IMG 6708

Highlights from a recent panel session moderated by Ed Sperling (Semiconductor Engineering) featuring Walden Rhines (Silvaco), Vincent Wong (Verific), Dave Kelf (Breker Verification Systems), Shelly Henry (MooresLab AI), Ann Wu (Silimate), and Cindy Cui (ChipAgents). The panel session was hosted by Electronic System … Read More


How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler

How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler
by Daniel Nenni on 06-12-2026 at 6:00 am

Kurt Shuler

Arteris is one of the most impressive companies SemiWiki has worked with over the last fifteen years. We have collaborated on one hundred and seventy-three articles/podcasts that have garnered more than two million views/listens. The success of Arteris can be easily tracked to the executive team and Kurt Shuler was the executive… Read More


WEBINAR: Engineering Documentation is a Critical Source of Truth – Do You Know if it’s Accurate?

WEBINAR: Engineering Documentation is a Critical Source of Truth – Do You Know if it’s Accurate?
by Mike Gianfagna on 06-11-2026 at 8:00 am

llmda homepage block (2)

Embedded systems programs rarely fail because of a lack of execution capability. They fail because critical engineering documentation drifts out of alignment over time and distance. Simply put, the team is correctly following the wrong instructions. This includes requirements, architecture, implementation, verification,… Read More


What’s New at the 2026 DAC Exhibits

What’s New at the 2026 DAC Exhibits
by Daniel Payne on 06-10-2026 at 10:00 am

dac26 barter ad semi 400 01

The most common question that I get each year at DAC is, “So, what’s new?” When I reviewed the exhibitor list I was pleasantly surprised to see how many EDA, IP and AI companies were attending that I didn’t know about. Here’s just a quick preview of what to expect in Long Beach from July 27-29. I’ll… Read More


Optimizing Photonic Integrated Circuit Production with yieldHUB Analytics

Optimizing Photonic Integrated Circuit Production with yieldHUB Analytics
by Daniel Nenni on 06-10-2026 at 8:00 am

Photonics yieldHUB 2026

As Photonic Integrated Circuits (PIC) continue to gain momentum across datacom, telecom, AI infrastructure, sensing, and quantum computing applications, the need for advanced manufacturing analytics has become increasingly critical. To address the challenges associated with scaling PIC production while maintaining… Read More


Customized Foundation IP Enables the Next Generation of Automotive Compute

Customized Foundation IP Enables the Next Generation of Automotive Compute
by Kalar Rajendiran on 06-09-2026 at 10:00 am

chip design for blog

As vehicles become increasingly software-defined, automotive semiconductor suppliers face growing pressure to deliver higher compute performance while maintaining strict requirements for power efficiency, reliability, and long-term product support. Advanced driver assistance systems (ADAS), electrification, … Read More


From Evidence to Authority: Bounded Gate Authority for Governed Semiconductor Realization

From Evidence to Authority: Bounded Gate Authority for Governed Semiconductor Realization
by Moh Kolb on 06-09-2026 at 6:00 am

Picture1 BGA JUne2

Advanced semiconductor systems are no longer limited by a single engineering domain. They are constrained by the convergence of many interdependent vectors: silicon nodes, advanced packaging architectures, substrate materials, platform PCBs, power-delivery networks, thermal behavior, manufacturing variation, firmware… Read More