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Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena

Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena
by Daniel Nenni on 07-10-2026 at 2:00 pm
Categories: EDA, Siemens EDA

Daniel is joined by Sagar Saxena, Senior Product Engineer at Siemens EDA specializing in computational lithography, optical proximity correction (OPC), and advanced patterning solutions for leading-edge semiconductor manufacturing. Sagar has led the development and deployment of advanced OPC technologies, including… Read More

July 10, 2026July 10, 2026

CEO Interview with Mark Ren of Agentrys

CEO Interview with Mark Ren of Agentrys
by Daniel Nenni on 07-10-2026 at 10:00 am
Categories: Agentrys, CEO Interviews, EDA

Mark Ren has 26 years of EDA and AI R&D experience spanning IBM Research and NVIDIA Research, driving design automation innovations that power modern chip design. He received the IBM Corporate Award for contributions to the design closure for high-performance microprocessors. At NVIDIA, he helped establish the company

July 9, 2026July 9, 2026

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise
by Daniel Nenni on 07-09-2026 at 10:00 am
Categories: EDA, Semiconductor Services

Electronic Design Automation, or EDA, is the software infrastructure that transforms a hardware specification into a manufacturable integrated circuit. At advanced process nodes, the problem is no longer simply drawing transistors or connecting gates. A modern system-on-chip contains billions of standard cells, hundreds… Read More

July 9, 2026July 9, 2026

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA
by ChandraM on 07-09-2026 at 6:00 am
Categories: AI, EDA

Over the last year, the EDA industry has started using a new vocabulary: agents, super agents, mental models, native skills, playbooks, RAG, MCP, autonomous workflows, and AI-first design.

The language is new, but the motivation is familiar to anyone who has worked in chip design.

Design complexity keeps increasing. The number… Read More

July 8, 2026July 9, 2026

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative
by Daniel Nenni on 07-08-2026 at 2:00 pm
Categories: EDA, Events, Moores Lab (AI)

For decades, semiconductor innovation has been constrained not by imagination, but by engineering capacity. While transistor density has continued to advance, the process of building chips has remained fundamentally manual, fragmented across specifications, RTL, verification, debugging, coverage analysis, and signoff.… Read More

July 8, 2026July 3, 2026

IP Lifecycle Management in the AI Era

IP Lifecycle Management in the AI Era
by Bernard Murphy on 07-08-2026 at 6:00 am
Categories: AI, EDA, Perforce

designer trying to find best IP options in a tangle of choices

Large design enterprises have multiple concurrent activities around IP of various types: software/firmware, blocks defined in RTL or HLS, verification IPs of multiple different types, physical implementations, scripts/files for timing, power management, etc., etc. Each of these continues to evolve and branch to serve … Read More

July 7, 2026July 9, 2026

See Autonomous Chip Design in Action with ChipAgents at DAC 2026

See Autonomous Chip Design in Action with ChipAgents at DAC 2026
by Daniel Nenni on 07-07-2026 at 2:00 pm
Categories: ChipAgents AI, EDA

Making the AI wave at DAC 2026 in Long Beach

DAC comes to Long Beach for the first time in 2026, with artificial intelligence expected to be one of the central topics across the conference program and exhibition floor.

For semiconductor design and verification teams, the discussion has moved beyond whether AI can assist engineers.… Read More

July 7, 2026July 7, 2026

Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026

Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026
by Daniel Nenni on 07-07-2026 at 6:00 am
Categories: Easy-Logic, EDA

Easy-Logic, a leading provider of high-performance Engineering Change Order (ECO) solutions in Electronic Design Automation (EDA), will showcase its latest innovation — the EasyAI ECO Suite — at DAC in Los Angeles, July 27–29, 2026. This intelligent ECO solution integrates AI engines into the entire ECO workflow and systematically… Read More

July 6, 2026July 6, 2026

From Detection to Safety: Reframing Fault Simulation for Functional Safety

From Detection to Safety: Reframing Fault Simulation for Functional Safety
by Lauro Rizzatti on 07-06-2026 at 10:00 am
Categories: EDA, Synopsys

In the early 1980s, when computer-aided engineering (CAE), the precursor to modern electronic design automation (EDA), was just taking shape, my professional trajectory shifted in a way that would prove foundational. I joined Teradyne, the Boston-based leader in automated test equipment (ATE), and I encountered for the first… Read More

Podcast EP353: What Real-Time Visibility Is and Why it Matters with yieldHUB’s John O’Donnell

Podcast EP353: What Real-Time Visibility Is and Why it Matters with yieldHUB’s John O’Donnell
by Daniel Nenni on 07-03-2026 at 2:00 pm
Categories: Analytics, EDA, yieldHUB

Daniel is joined by John O’Donnell, Founder and CEO of yieldHUB, a pioneering leader in advanced data analytics for the semiconductor industry. Since establishing the company in 2005 he has transformed it from a two-person startup into a trusted multinational partner that empowers some of the world’s leading semiconductor … Read More

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
HPC can be Chiplet. Wondering why UCIe is not considered. Internally AMBA neither

— chiro.lentz on July 11, 2026
The Packaging PDK Is the Missing Layer for Co-Packaged Optics
Thank you to Daniel Nenni and SemiWiki for publishing my latest article: The Packaging PDK Is the Missing Layer for…

— moh.kolb on July 8, 2026
The Packaging PDK Is the Missing Layer for Co-Packaged Optics
Very interesting. Thanks.

— U235 on July 8, 2026
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031
N+3 is denser than N6: https://newsletter.semianalysis.com/p/steel-smic-n3-teardown?open=false

— Fred Chen on July 5, 2026
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031
Fixed, thank you.

— Daniel Nenni on July 4, 2026
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031
The article is not correct. EUV equipment is not primarily produced by ASML. It is only produced by ASML. It…

— AndyG on July 4, 2026
Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?
Nice writeup

— Rahul Razdan on June 27, 2026
Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs
In a DoD centric III-V fab I had wafers run in a few decades ago, yield was miserable, but adequate…

— PBealo on June 27, 2026

Webinar: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

Webinar: Scaling Compute Connectivity with PCIe and CXL: Chip-to-Chip and Emerging Architectures

Advanced Packaging Summit 2026

Webinar: Formal Verification for Non-Specialists

10th Edition — IEEE International Test Conference INDIA 2026

Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena

CEO Interview with Mark Ren of Agentrys

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative

IP Lifecycle Management in the AI Era

See Autonomous Chip Design in Action with ChipAgents at DAC 2026

Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026

From Detection to Safety: Reframing Fault Simulation for Functional Safety

Podcast EP353: What Real-Time Visibility Is and Why it Matters with yieldHUB’s John O’Donnell

Recent Forum Threads

Japan’s Rapidus Takes on TSMC With Aggressive 2nm Pricing

Nvidia, CoreWeave, and Nebius: Inside the Circular Financing of the GPU Boom

U.S.-backed chip startup xLight aims to raise $350 million for an EUV alternative

Taiwanese chipmaker Nanya plans $6 billion in spending in 2027, riding AI boom

WSJ: Apple avoided semiconductor tariffs last year thanks to Intel chip deal

EMI Is the Disturbance. EMC Is the Evidence. by Dr. Moh Kolbehdari

Why CPUs Are Now at the Center of the AI Race

Apple Sues OpenAI for Stealing Trade Secrets, Latter’s IPO Valuation Logic to Face Clear Pressure

The White House Made Fixing Intel Its Pet Project. It’s Working Wall Street Journal

Apple to spend $30 billion on Broadcom chips as it boosts US sourcing

Recent Article Comments

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

The Packaging PDK Is the Missing Layer for Co-Packaged Optics

The Packaging PDK Is the Missing Layer for Co-Packaged Optics

Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031

Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031

Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031

Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?

Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs