IMGTC Webinar SemiWIki
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4598
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4598
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

OpenAI and Synopsys Announce GPT-Synopsys: Why AI-Powered Chip Design Matters

OpenAI and Synopsys Announce GPT-Synopsys: Why AI-Powered Chip Design Matters
by Daniel Nenni on 10-01-2026 at 8:00 am

Synopsys OpenAI

Wow, OpenAI and Synopsys just announced a multiyear partnership to develop GPT-Synopsys, a specialized artificial intelligence model for semiconductor design. The agreement combines OpenAI’s frontier models with Synopsys’ electronic design automation software and engineering expertise. Its ambition is to help engineers… Read More


Quantum Equivalence Checking. Innovation in Verification

Quantum Equivalence Checking. Innovation in Verification
by Bernard Murphy on 09-30-2026 at 6:00 am

Innovation New

Can quantum computing have any relevance to EDA? This month’s paper suggests it might have a role someday, in accelerating one of the most fundamental of EDA algorithms: SAT. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More


Why Advanced Chip Packaging Is Becoming a Design Problem

Why Advanced Chip Packaging Is Becoming a Design Problem
by Daniel Nenni on 09-29-2026 at 2:00 pm

Why Advanced Chip Packaging Is Becoming a Design Problem

As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die… Read More


Managing Power, Performance and Reliability in the Chiplet Era

Managing Power, Performance and Reliability in the Chiplet Era
by Kalar Rajendiran on 09-29-2026 at 10:00 am

Test Drivers proteanTecs (Chiplet Webinar)

Next-gen AI accelerators, high-performance processors, and complex computing architectures depend heavily on advanced packaging. Bringing multiple dies, chiplets, high-bandwidth memory, and advanced interconnects together into a single 2.5D or 3D package yields massive performance gains. However, this design evolution… Read More


Siemens and TSMC push AI deeper into chip design

Siemens and TSMC push AI deeper into chip design
by Daniel Nenni on 09-29-2026 at 8:00 am

Siemens and TSMC push AI deeper into chip design

Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from… Read More


Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?

Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?
by Moh Kolb on 09-29-2026 at 6:00 am

AgentiC AI SemiWIKI sept21

Agentic AI is beginning to move semiconductor engineering beyond copilots and isolated task automation.

From Agentrys’ public material and recent discussion, its architecture points toward a broader engineering flow:

Specification → RTL → verification → synthesis / physical design → PPA optimization → physical verification… Read More


LLM-assisted schematic test-report analysis and root-cause investigation

LLM-assisted schematic test-report analysis and root-cause investigation
by Admin on 09-28-2026 at 10:00 am

schematic report workflow white (1)

By Piyush Bag

Intro: In this AI era, building data centers has become crucial not just for hyperscalers, but for many companies as well, as they build the infrastructure for AI. At a high level, a data center includes compute, storage, networking, and other infrastructure. This article is about the design lifecycle of network hardware.… Read More


From Frontend to the Frontiers of Silicon with Moores Lab AI

From Frontend to the Frontiers of Silicon with Moores Lab AI
by Daniel Nenni on 09-28-2026 at 8:00 am

Alex
Alex Navarro is a Principal Software Engineer at Moores Lab AI, where he was the company’s first engineering hire. He spent about ten years in frontend development before moving into semiconductors. Since then he has helped grow Moores Lab AI from an early prototype into a full ecosystem of agentic products that covers the
… Read More

Synopsys Announces AgentEngineer Solutions and Autopilot Platform for Autonomous Engineering

Synopsys Announces AgentEngineer Solutions and Autopilot Platform for Autonomous Engineering
by Kalar Rajendiran on 09-28-2026 at 6:00 am

updated from ai assisants to autonomous engineering

Synopsys today announced its AgentEngineerTM solutions portfolio and AutopilotTM Platform, advancing a fundamental paradigm shift in electronic design automation (EDA): moving beyond AI copilots toward autonomous engineering agents. Following a recent technical briefing with Thomas Andersen, Vice President of AI and… Read More


PDF Solutions CONNECT, the Premier Event for Semiconductor Analytics and AI, October 15 and 16 in San Francisco

PDF Solutions CONNECT, the Premier Event for Semiconductor Analytics and AI, October 15 and 16 in San Francisco
by Daniel Nenni on 09-27-2026 at 12:00 pm

AI Agent Breaches in 2026

On October 15 and 16, 2026, in San Francisco, PDF Solutions will hold PDF Solutions CONNECT, the premier event for Semiconductor Analytics and AI. This event starts at the end of SEMICON WEST 2026 in a location in close proximity to the Moscone Center. It is a great opportunity for leading semiconductor and equipment companies attending… Read More