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EDA

Electronic Design Automation

Podcast EP337: The Importance of Network Communications to Enable AI Workloads with Abhinav Kothiata

Podcast EP337: The Importance of Network Communications to Enable AI Workloads with Abhinav Kothiata
by Daniel Nenni on 03-27-2026 at 10:00 am
Categories: EDA, IP, Synopsys

Daniel is joined by Abhinav Kothiata, a principal product manager for the Synopsys Ethernet IP portfolio. He has over 12 years of experience across engineering and product management, spanning SoC design, functional verification, and building wireless connectivity platforms and IoT products. He also holds two patents in … Read More

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Synopsys Advances Hardware Assisted Verification for the AI Era

Synopsys Advances Hardware Assisted Verification for the AI Era
by Kalar Rajendiran on 03-26-2026 at 6:00 am
Categories: 3D IC, AI, Chiplet, EDA, Emulation, FPGA, IP, Prototyping, Synopsys, Xilinx

Software Defined HAV, Scalability, Density, Performance and EP Ready Hardware

At the 2026 Synopsys Converge Event, Synopsys announced a broad set of new products and platform upgrades, with its hardware-assisted verification (HAV) announcement emerging as a key highlight within that lineup. A key aspect of this announcement was moving beyond a hardware centric model to a more scalable, programmable … Read More

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Post-Silicon Validating an MMU. Innovation in Verification

Post-Silicon Validating an MMU. Innovation in Verification
by Bernard Murphy on 03-25-2026 at 6:00 am
Categories: Cadence, EDA, Semiconductor Services, Silicon Catalyst

Innovation New

Some post-silicon bugs are unavoidable, but we’re getting better at catching them before we ship. Here we look at a method based on a bare-metal exerciser to stress-test the MMU. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More

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Securing UALink in AI clusters with UALinkSec-compliant IP

Securing UALink in AI clusters with UALinkSec-compliant IP
by Don Dingee on 03-24-2026 at 10:00 am
Categories: AI, IP, Synopsys

UALinkSec 200 Security Module block diagram

A classic networking problem is securing connections with encrypted data, but implementing strong encryption algorithms at wire speeds can limit performance. However, introducing blazing-fast connectivity without an encryption strategy leaves systems vulnerable. The architects in the UALink Consortium, including … Read More

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Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
by Kalar Rajendiran on 03-23-2026 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Synopsys

Bump maps for HBM PHY and HBM memory

This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the Interconnect… Read More

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WEBINAR: Reclaiming Clock Margin at 3nm and Below

WEBINAR: Reclaiming Clock Margin at 3nm and Below
by Daniel Nenni on 03-19-2026 at 2:00 pm
Categories: ClockEdge, EDA, Events

Webinar Blog Image Reclaiming Clock Margin

At 3nm and below, clock networks have quietly become the dominant limiter of SoC power, performance, and yield. Yet most advanced-node designs still rely on abstraction-based signoff methodologies developed when voltage headroom was generous and interconnect effects were secondary.

That assumption no longer holds

As supply… Read More

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Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement
by Mike Gianfagna on 03-19-2026 at 8:00 am
Categories: 3D IC, EDA, Events, Siemens EDA

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Enablement

The recent Chiplet Summit in Santa Clara was buzzing with new designs and new design methods. It felt like the industry had turned a corner at this year’s event with lots of new technology and design success on display. Siemens EDA had a large presence at the show and took home the Best in Show Award for Packaging Design. There were a … Read More

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Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design

Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design
by Bernard Murphy on 03-19-2026 at 6:00 am
Categories: AI, EDA, Siemens EDA

Fuse Agentic System

Though terminology sometimes get fuzzy, consensus holds that an agent manages a bounded task with control through a natural language interface. An agentic orchestrator, itself an agent, manages a more complex objective requiring reasoning through multi-step actions and is responsible for orchestrating those actions. By… Read More

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Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer

Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer
by Kalar Rajendiran on 03-18-2026 at 10:00 am
Categories: EDA, Lithography, Siemens EDA

Rasterization Polygon to pixel based representation

As semiconductor manufacturing pushes deeper into the nanometer regime, computational lithography has evolved from a supporting step into a central pillar of advanced chip design. Mask synthesis, lithography simulation, and optical proximity correction (OPC) now demand unprecedented levels of accuracy and computational… Read More

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Verification Analytics: The New Paradigm with Cogita-PRO at DVCON 2026

Verification Analytics: The New Paradigm with Cogita-PRO at DVCON 2026
by Daniel Nenni on 03-18-2026 at 8:00 am
Categories: EDA, Events

The Cogita PRO Paradigm

Cogita-PRO, developed by Vtool, introduces a transformative approach to design verification by treating it as a big data challenge rather than a traditional debugging exercise. Released in February 2026, this tool shifts the focus from manual log and waveform inspection to advanced verification analytics powered by data … Read More