Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Podcast EP317: A Broad Overview of Design Data Management with Keysight’s Pedro Pires

Podcast EP317: A Broad Overview of Design Data Management with Keysight’s Pedro Pires
by Daniel Nenni on 11-14-2025 at 10:00 am

Daniel is joined by Pedro Pires, a product and technology leader with a strong background in IP and data management within the EDA industry. Currently a product manager at Keysight Technologies, he drives the roadmap for the AI-driven data management solutions. Pedro’s career spans roles in software engineering and data science… Read More


WEBINAR: Revolutionizing Electrical Verification in IC Design

WEBINAR: Revolutionizing Electrical Verification in IC Design
by Daniel Nenni on 11-13-2025 at 10:00 am

Electrical Verification – The invisible bottleneck in IC design 2

In the complex world of IC design, electrical verification has emerged as a critical yet often overlooked bottleneck. Aniah’s upcoming webinar on December 4, 2025, titled “Electrical Verification: The Invisible Bottleneck in IC Design,” sheds light on this issue, introducing their groundbreaking OneCheck® solution. … Read More


Hierarchically defining bump and pin regions overcomes 3D IC complexity

Hierarchically defining bump and pin regions overcomes 3D IC complexity
by Admin on 11-13-2025 at 8:00 am

connectivity in a hierarchical IC package floorplan

By Todd Burkholder and Per Viklund, Siemens EDA

The landscape of advanced IC packaging is rapidly evolving, driven by the imperative to support innovation on increasingly complex and high-capacity products. The broad industry trend toward heterogeneous integration of diverse die and chiplets into advanced semiconductor… Read More


CDC Verification for Safety-Critical Designs – What You Need to Know

CDC Verification for Safety-Critical Designs – What You Need to Know
by Mike Gianfagna on 11-13-2025 at 6:00 am

CDC Verification for Safety Critical Designs – What You Need to Know

Verification is always a top priority for any chip project. Re-spins result in lost time-to-market and significant cost overruns. Chip bugs that make it to the field present another level of lost revenue, lost brand confidence and potential costly litigation. If the design is part of the avionics or control for an aircraft, the… Read More


EDA Has a Value Capture Problem — An Outsider’s View

EDA Has a Value Capture Problem — An Outsider’s View
by Admin on 11-11-2025 at 10:00 am

Figure1 (1)

By Liyue Yan (lyan1@bu.edu)

Fact 1: In the Computer History Museum, how many artifacts are about Electronic Design Automation (EDA)? Zero.

Fact 2: The average starting base salary for a software engineer at Netflix is $219K, and that number is $125K for Cadence; the starting base salary for a hardware engineer at Cadence is $119K… Read More


WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity

WEBINAR: How PCIe Multistream Architecture is Enabling AI Connectivity
by Daniel Nenni on 11-11-2025 at 8:00 am

multistream webinar banner square

In the race to power ever-larger AI models, raw compute is only half the battle. The real challenge lies in moving massive datasets between processors, accelerators, and memory at speeds that keep up with trillion-parameter workloads. Synopsys tackles this head-on with its webinar, How PCIe Multistream Architecture is EnablingRead More


Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution

Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution
by Lauro Rizzatti on 11-10-2025 at 10:00 am

Lessons from the DeepChip wars Table

The competitive landscape of hardware-assisted verification (HAV) has evolved dramatically over the past decade. The strategic drivers that once defined the market have shifted in step with the rapidly changing dynamics of semiconductor design.

Design complexity has soared, with modern SoCs now integrating tens of billions… Read More


Video EP11: Meeting the Challenges of Superconducting Quantum System Design with Mohamed Hassan

Video EP11: Meeting the Challenges of Superconducting Quantum System Design with Mohamed Hassan
by Daniel Nenni on 11-07-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series,  Dan is joined by Mohamed Hassan, who leads the Quantum EDA segment at Keysight. Mohamed provides a broad overview of superconducting quantum system design. He discusses the challenges for this design style and how EDA requirements for quantum design differ from
Read More

AI RTL Generation versus AI RTL Verification

AI RTL Generation versus AI RTL Verification
by Bernard Murphy on 11-06-2025 at 10:00 am

RTL generation vs RTL Verification

I should admit up front that I don’t have a scientific answer to this comparison, but I do have a reasonably informed gut feel, at least for the near-term. The reason I ask the question is that automated RTL generation grabs headlines with visions of designing chips through natural language prompts, making design widely accessible.… Read More


5 Lessons the Semiconductor Industry Can Learn from Gaming

5 Lessons the Semiconductor Industry Can Learn from Gaming
by Admin on 11-05-2025 at 10:00 am

Perforce 1

By Kamal Khan
The semiconductor world has always been the beating heart of tech innovation, powering everything from our smartphones to the latest AI breakthroughs. However, as chip complexity increases and market demands accelerate, adherence to traditional development cycles may be stagnating design teams and slowing … Read More