RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4446
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4446
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Podcast EP340: A Review of the Q4 2025 Electronic Design Market Data Report with Wally Rhines

Podcast EP340: A Review of the Q4 2025 Electronic Design Market Data Report with Wally Rhines
by Daniel Nenni on 04-13-2026 at 8:00 am

Daniel is joined by Dr. Wally Rhines, CEO of Silvaco, to discuss the Electronic Design Market Data report that was just released. Wally is the industry coordinator for the EDA data collection program called EDMD. SEMI and the Electronic System Design Alliance collect data from almost all electronic design automation companies… Read More


From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is Unfolding

From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is Unfolding
by Lauro Rizzatti on 04-13-2026 at 6:00 am

From Wooden Boards to White Gloves Table 1 (1)

FPGA prototyping and hardware emulation originated from two independent demands that emerged at roughly the same time, namely, the necessity to implement digital designs in reconfigurable hardware. This was conceivable given the newly introduced field programmable gate array (FPGA) device.

Yet from the very beginning they… Read More


yieldHUB Expands Its Impact with New Technology and a New Website

yieldHUB Expands Its Impact with New Technology and a New Website
by Mike Gianfagna on 04-09-2026 at 10:00 am

yieldHUB Expands Its Impact with New Technology and a New Website

yieldHUB is a unique company that focuses on yield optimization for the semiconductor industry. The company aims to bring engineering teams together with a platform that allows sharing of data analytics and knowledge about products to improve yield. This goal is certainly fueled by unifying data from multiple steps in the manufacturing… Read More


From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration

From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration
by Daniel Nenni on 04-08-2026 at 10:00 am

Types of Mutli Deisgn Packaging Synsopsys

Modern automotive electronics are undergoing a rapid transformation driven by increasing compute demands, functional safety requirements, and the shift toward scalable semiconductor architectures. One of the most significant technological developments enabling this transformation is the adoption of multi-die system… Read More


WEBINAR: Beyond Moore’s Law and The Future of Semiconductor Manufacturing Intelligence

WEBINAR: Beyond Moore’s Law and The Future of Semiconductor Manufacturing Intelligence
by Daniel Nenni on 04-06-2026 at 10:00 am

The Future of Semiconductor Manufacturing Intelligence

The semiconductor industry faces unprecedented challenges as it pushes toward advanced nodes below 3nm, managing exponential process complexity, yield variability, and escalating production costs.

This webinar explores the transition from reactive automation to autonomous manufacturing, bringing together leaders… Read More


yieldWerx Delivers a Master Class in Co-Packaged Photonics Implementation

yieldWerx Delivers a Master Class in Co-Packaged Photonics Implementation
by Mike Gianfagna on 04-06-2026 at 10:00 am

yieldWerx Delivers a Master Class in Co Packaged Photonics Implementation

We all know the semiconductor industry is seeing a new era of data intensity. The industry’s response includes advanced semiconductor design strategies, the adoption of chiplets, and the integration of optical I/O and photonics to enable higher performance, faster AI computation, and increased modularity. Co-packaged photonics… Read More


Webinar – How to Reclaim Margin in Advanced Nodes

Webinar – How to Reclaim Margin in Advanced Nodes
by Mike Gianfagna on 04-02-2026 at 6:00 am

Webinar – How to Reclaim Margin in Advanced Nodes

This informative webinar discusses a significant issue that is cropping up for sub-5nm designs. As the graphic above shows, modeling uncertainty at advanced nodes results in excessive guard banding. These guard bands result in reduced performance and profit. A loss of 25 – 35% in PPA is discussed, along with the lost profit associated… Read More


Podcast EP337: The Importance of Network Communications to Enable AI Workloads with Abhinav Kothiala

Podcast EP337: The Importance of Network Communications to Enable AI Workloads with Abhinav Kothiala
by Daniel Nenni on 03-27-2026 at 10:00 am

Daniel is joined by Abhinav Kothiala, a principal product manager for the Synopsys Ethernet IP portfolio. He has over 12 years of experience across engineering and product management, spanning SoC design, functional verification, and building wireless connectivity platforms and IoT products. He also holds two patents in… Read More


Synopsys Advances Hardware Assisted Verification for the AI Era

Synopsys Advances Hardware Assisted Verification for the AI Era
by Kalar Rajendiran on 03-26-2026 at 6:00 am

Software Defined HAV, Scalability, Density, Performance and EP Ready Hardware

At the 2026 Synopsys Converge Event, Synopsys announced a broad set of new products and platform upgrades, with its hardware-assisted verification (HAV) announcement emerging as a key highlight within that lineup. A key aspect of this announcement was moving beyond a hardware centric model to a more scalable, programmable … Read More


Post-Silicon Validating an MMU. Innovation in Verification

Post-Silicon Validating an MMU. Innovation in Verification
by Bernard Murphy on 03-25-2026 at 6:00 am

Innovation New

Some post-silicon bugs are unavoidable, but we’re getting better at catching them before we ship. Here we look at a method based on a bare-metal exerciser to stress-test the MMU. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More