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Defacto Technologies and ARM, Joint SoC Flow at #61DAC

Defacto Technologies and ARM, Joint SoC Flow at #61DAC
by Daniel Payne on 07-31-2024 at 10:00 am

arm defacto 61dac min

At #61DAC I stopped by the Defacto Technologies exhibit and talked with Chouki Aktouf, President and CEO, to find out what’s new in 2024. ARM and Defacto have a joint SoC design flow by using the Arm IP Explorer tool along with Defacto’s SoC compiler, which helps to quickly create your top-level RTL, IP-XACT and UPF files. This tool… Read More


A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC

A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC
by Daniel Nenni on 07-23-2024 at 6:00 am

flow ip explorer soc compiler (1)

When I was at DAC last month, I had the chance to talk with Chouki Aktouf and Bastien Gratréaux from Defacto and they told me about a new innovative solution to generate Arm-based System-on-Chips. I heard that this solution has now been released.

Defacto and Arm developed a joint SoC design flow to help Arm users cover all needed automation—from… Read More


Innova at the 2024 Design Automation Conference

Innova at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 12:00 pm

DAC 2024 Banner

Design projects are becoming more and more complex. The success of a design project is tightly linked to the best preparation. Having an accurate and precise prediction of either project design resources or design parameters, with a plan to react in an appropriate way is crucial and cost saving.

A typical example is the availability… Read More


Defacto at the 2024 Design Automation Conference

Defacto at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 10:00 am

DAC 2024 Banner

Defacto continues to confirm its SoC Compiler as becoming the “de facto” SoC integration solution for large SoC designs. This year they are coming to DAC to share customer success stories of building the largest SoCs in the market from specification to RTL + collaterals such as UPF by including thousands of IP cores! All done within… Read More


WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
by Daniel Nenni on 12-11-2023 at 10:00 am

Blog UPF Picture1

Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.

WEBINAR REGISTRATION

With the increasing complexity of such … Read More


Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology

Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology
by Daniel Nenni on 10-03-2023 at 6:00 am

blog sept pic1

With the increasing on-chip integration capabilities, large scale electronic systems can be integrated into a single System-on-Chip or SoC. New manufacturing test challenges are raised for more advanced technology nodes where both quality and cost during testing are affected. A typical parameter is test coverage which impacts… Read More


Defacto Celebrates 20th Anniversary @ DAC 2023!

Defacto Celebrates 20th Anniversary @ DAC 2023!
by Daniel Nenni on 07-05-2023 at 10:00 am

20ans signature clean

Defacto Technologies is a company that specializes in Electronic Design Automation (EDA) software and solutions. Defacto offers a range of EDA software solutions that help streamline and optimize various stages of the front-end design process. Their tools focus on chip design assembly and integration before logic synthesis

Read More

WEBINAR: Design Cost Reduction – How to track and predict server resources for complex chip design project?

WEBINAR: Design Cost Reduction – How to track and predict server resources for complex chip design project?
by Daniel Nenni on 04-11-2023 at 6:00 am

picture innova

During the design of complex chips, cost reduction is becoming a real challenge for small, medium and large companies.  Resource management is a key to contain design cost.

The chip design market is expecting automated solutions to help in the resource prediction, planning and analysis. AI-based technologies are promising … Read More


Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy

Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy
by Daniel Nenni on 03-02-2023 at 6:00 am

SoC Integration IP XACT RTL

We have been working with Defacto since 2016 and it has been quite a journey. Putting an entire system on a chip is a driving force in the semiconductor industry. With the complexity of designing a modern SoC constantly increasing, new tools and methodologies are required and it all starts with RTL.

Defacto Technologies is an innovativeRead More


Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More