Defacto continues to confirm its SoC Compiler as becoming the “de facto” SoC integration solution for large SoC designs. This year they are coming to DAC to share customer success stories of building the largest SoCs in the market from specification to RTL + collaterals such as UPF by including thousands of IP cores! All done within… Read More
WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.
With the increasing complexity of such … Read More
Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology
With the increasing on-chip integration capabilities, large scale electronic systems can be integrated into a single System-on-Chip or SoC. New manufacturing test challenges are raised for more advanced technology nodes where both quality and cost during testing are affected. A typical parameter is test coverage which impacts… Read More
Defacto Celebrates 20th Anniversary @ DAC 2023!
Defacto Technologies is a company that specializes in Electronic Design Automation (EDA) software and solutions. Defacto offers a range of EDA software solutions that help streamline and optimize various stages of the front-end design process. Their tools focus on chip design assembly and integration before logic synthesis
WEBINAR: Design Cost Reduction – How to track and predict server resources for complex chip design project?
During the design of complex chips, cost reduction is becoming a real challenge for small, medium and large companies. Resource management is a key to contain design cost.
The chip design market is expecting automated solutions to help in the resource prediction, planning and analysis. AI-based technologies are promising … Read More
Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy
We have been working with Defacto since 2016 and it has been quite a journey. Putting an entire system on a chip is a driving force in the semiconductor industry. With the complexity of designing a modern SoC constantly increasing, new tools and methodologies are required and it all starts with RTL.
Defacto Technologies is an innovative… Read More
Using IP-XACT, RTL and UPF for Efficient SoC Design
The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More
Working with the Unified Power Format
The Accellera organization created the concept of a Unified Power Format (UPF) back in 2006, and by 2007 they shared version 1.0 so that chip designers would have a standard way to communicate the power intentions of IP blocks and full chips. By 2009 the IEEE received the Accellera donation on UPF , reviewed multiple drafts and published… Read More
Webinar – How to manage IP-XACT complexity in conjunction with RTL implementation flow
Standards help our EDA and IP industry grow more quickly and with less CAD integration efforts, and IP-XACT is another one of those Accellera standards (1685-2009) that is coming of age, and enabling IP reuse for SoC design teams. Here at SemiWik, we’ve been writing about Defacto Technologies and their prominent use of IP-XACT… Read More
WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?
Defacto SoC Compiler whose 9.0 release was announced recently automates the SoC design creation from the first project specifications. It covers register handling, IP and connectivity insertion at RTL, UPF and SDC file generation right to logic synthesis. As part of the generation process of RTL and design collaterals, basic… Read More

