The Electronic Design Automation (EDA) industry used to be a bustling bazaar of scrappy startups, along with medium sized companies that dominated a technology space, and big main-line vendors. The annual Design Automation Conference was noisy, hectic, and sprawled over multiple large convention halls. This diversity meant… Read More
CEO Interview: Mo Faisal of Movellus
Prior to founding Movellus, Dr. Faisal held positions at semiconductor companies such as Intel and PMC Sierra. Faisal received his B.S. from the University of Waterloo, and his M.S. and Ph.D. from the University of Michigan, and holds several patents. Dr. Faisal was named a “Top 20 Entrepreneur” by the University of Michigan Zell… Read More
System Technology Co-Optimization (STCO)
My first exposure to seeing multiple die inside of a single package in order to get greater storage was way back in 1978 at Intel, when they combined two 4K bit DRAM die in one package, creating an 8K DRAM chip, called the 2109. Even Apple used two 16K bit DRAM chips from Mostek to form a 32K bit DRAM, included in the Apple III computer, circa… Read More
Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum
The TSMC Open Innovation Platform (OIP) event brings together a wide array of companies reporting cutting edge work that are part of TSMC’s rather substantial ecosystem. The event covers everything from high-performance computing to mobile, automotive, IoT, RF and 3D IC design. Of particular interest for this post is a presentation… Read More
Update on TSMC’s 3D Fabric Technology
TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum. An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).
Overview of 3D Fabric
The TSMC… Read More
Optical I/O Solutions for Next-Generation Computing Systems
According to DARPA the fraction of total power consumed in semiconductors for I/O purposes as been growing rapidly and is creating an I/O power bottleneck. It has reached the point where it needs to be addressed with new technologies and approaches. Interestingly, while the energy density, as measured by pJ/bit for short reach… Read More
Design Planning and Optimization for 3D and 2.5D Packaging
Introduction
Frequent SemiWiki readers are aware of the growing significance of heterogeneous multi-die packaging technologies, offering a unique opportunity to optimize system-level architectures and implementations. The system performance, power dissipation, and area/volume (PPA/V) characteristics of a multi-die… Read More
Chiplet: Are You Ready For Next Semiconductor Revolution?
During the 2010-decade, the benefits of Moore’s law began to fall apart. Moore’s law stated transistor density doubled every two years, the cost of compute would shrink by a corresponding 50%. The change in Moore’s law is due to increased in design complexity the evolution of transistor structure from planar devices, to Finfets.… Read More
Expanding Intel’s Foundry Partnerships: A Critical Piece of IDM 2.0
One of the career Intel employees (33+ years) that Pat Gelsinger brought back is Stuart Pann. Stuart is now the Senior Vice President of the Intel Corporate Planning Group. He does not have direct foundry experience but he certainly knows Intel and Pat so it will be interesting to see where this goes.
Stuart recently penned an article… Read More
IPnest Forecast Interface IP Category Growth to $2.5B in 2025
Why should the interface IP category see such a high growth rate until 2025? IP vendors revenues totaled $1068 million in 2020, compared with $872 in 2019. That is 22.4% YoY growth rate and confirm that last year YoY value of 18% was the sign for a long-term growth, as IPnest shows in “Interface IP Survey 2016-2020 & Forecast 2021-2025”,… Read More
Semiconductors Slowing in 2025