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Artificial Intelligence
On July 18, 2025, a DACtv session titled “From Atoms to Tokens” explored the semiconductor supply chain’s transformation, as presented in the YouTube video. The speaker tackled the challenges and innovations from the atomic level of chip fabrication to the tokenized ecosystems of AI-driven data centers, emphasizing the critical… Read More
On July 18, 2025, Siemens EDA and Nvidia presented a compelling vision for the future of electronic design automation (EDA) at a DACtv event, emphasizing the transformative role of artificial intelligence (AI) in semiconductor and PCB design. Amit Gupta, Vice President and General Manager at Siemens EDA, and John Lynford, head… Read More
In a keynote at the 62nd Design Automation Conference (DAC) on July 8, 2025, William Chappell, Vice President of Mission Systems at Microsoft, reflected on the intertwined evolution of AI and semiconductor design. Drawing from his DARPA experience, Chappell traced AI’s progression from 2016 onward, highlighting its… Read More
In a DACtv session on July 9, 2025, Abhi Kolpekwar, Vice-President & General Manager at Siemens EDA, illuminated the transformative role of artificial intelligence (AI) in addressing the escalating challenges of semiconductor design verification. The presentation underscored the limitations of traditional methods… Read More
Designing a system-on-chip (SoC) has never been more complex—or more critical. With accelerating demands across AI, automotive, and high-performance compute applications, today’s SoC architects face a series of high-stakes tradeoffs from the very beginning. Decisions made during the earliest phases of design—regarding… Read More
AI’s exponential growth is transforming semiconductor design—and memory is now as critical as compute. Multi-die architecture has emerged as the new frontier, and custom High Bandwidth Memory (cHBM) is fast becoming a cornerstone in this evolution. In a panel session at the Synopsys Executive Forum, leaders from AWS, Marvell,… Read More
We have a shortage of reference designs to test detection of security vulnerabilities. An LLM-based method demonstrates how to fix that problem with structured prompt engineering. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More
Given my SpyGlass background I always keep an eye out for new ideas that might be emerging in static and formal verification. Whatever can be covered through stimulus-free analysis reduces time that needn’t be wasted in dynamic analysis, also adding certainty to coverage across that range. Still, advances don’t come easily. … Read More
In Silvaco’s July 2025 video presentation at the 62nd Design Automation Conference (DAC), Senior Staff Applications Engineer Tim Colton introduced Jivaro, a specialized parasitic reduction tool designed to tackle the escalating challenges of post-layout simulation in advanced IC designs. As semiconductor nodes… Read More
Matthew Addley is an Industry Strategist at Infor, specializing in the global manufacturing sector. With over 30 years of experience in driving business transformation through technology, he aligns industry needs with Infor’s product strategy through thought leadership, customer engagement, and market insight. Beginning… Read More
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AI RTL Generation versus AI RTL Verification