Formal Analysis of Security Data Paths

Formal Analysis of Security Data Paths
by Paul McLellan on 12-05-2012 at 5:07 pm

One challenge with security in systems is to ensure that there are not backdoors, either accidentally or maliciously inserted. Intel, ARM and others have various forms of trusted execution technology. Under the hood these are implemented by dividing the design into two parts, normal and secure, and implementing them with physical… Read More


Patents: Who to Sue?

Patents: Who to Sue?
by Paul McLellan on 12-05-2012 at 12:52 pm

In an interview (probably $) with the Wall Street Journal, Eric Schmidt, the chairman (and ex-CEO) of Google, said:“The adult way to run a business is to run it more like a country. They have disputes, yet they’ve actually been able to have huge trade with each other. They’re not sending bombs at each other. … It’s extremely curious… Read More


SystemC vs C++ for High Level Synthesis

SystemC vs C++ for High Level Synthesis
by Paul McLellan on 12-04-2012 at 4:00 pm

One of the decisions that needs to be made when using high-level synthesis (HLS) in general and Catapult in particular is what language to use as input. The choice is C++ or SystemC. Of course at some level SystemC is C++ with added libraries and templates, but in fact the semantics of the two languages end up being very different.

The… Read More


ST Microelectronics: Strategic Options

ST Microelectronics: Strategic Options
by Paul McLellan on 12-01-2012 at 5:11 pm

ST Microelectronics announced yesterday that it would have a conference call on December 10th to announce its strategy going forward. ST has been struggling the last couple of years, with revenues down year to year. From 2010-2012 (the last an estimate of course) it did $10.3B, $9.6B and $8.4B so it has shrunk nearly 20% in 3 years.… Read More


Accelera Technical Excellence Award

Accelera Technical Excellence Award
by Paul McLellan on 11-30-2012 at 3:46 pm

The Accellera Systems Initiative, most well-known for driving the standardization of various aspects of Verilog and SystemVerilog before handing the standards off to the IEEE, has announced that nominations are open for the 2013 Technical Excellence Award. This recognizes outstanding contributions in the creation of EDA… Read More


Challenges of Implementing LTE

Challenges of Implementing LTE
by Paul McLellan on 11-30-2012 at 3:07 pm

LTE (Long Term Evolution) is the true 4G standard for cellular and, over time, wireless internet. In fact it is several different standards with different levels of performance. LTE will eventually be the only technology used in cellular, voice will simply be Voice-over-IP (VoIP, the same technology that companies like Skype… Read More


Sequential Power Optimization

Sequential Power Optimization
by Paul McLellan on 11-29-2012 at 8:44 pm

Calypto has an interesting webinar coming up about Minimizing RTL Power Through Sequential Analysis. It is next Tuesday December 4th at 11am.

Insert standard paragraph about how power is the new timing, everyone worries about power, battery life in smartphones, half-empty datacenters.

You probably already know about clock… Read More


Anyone Can Build a Phone

Anyone Can Build a Phone
by Paul McLellan on 11-27-2012 at 2:49 am

Today’s Dilbert cartoon is about how anybody can build a smart phone. As if it was a technical problem these days. But back in the mid-90s it really was. All the contract manufacturers like Solectron and others figured that since they could build a PC they could build a phone. It turned out that building radios was really hard.… Read More


Apache on Signal Integrity

Apache on Signal Integrity
by Paul McLellan on 11-20-2012 at 1:09 pm

Matt Elmore has a two-part blog about the growing complexity of signal integrity analysis, both on the chip itself and the increasingly complex analysis required to make sure that signals (and power) get in and out of the chip from the board cleanly, especially to memory, which requires simultaneous analysis of chip-package-system… Read More


EDS Fair: Dateline Yohohama

EDS Fair: Dateline Yohohama
by Paul McLellan on 11-20-2012 at 12:22 pm

Electronic Design and Solutions Fair (EDSF) was held in Yokohama Japan from Wednesday to Friday last week. It was held at the Pacifico Hotel, somewhere I have stayed several times, not far from the Yokohama branch of Hard Rock Cafe and, what used to be at least, the biggest ferris-wheel in the world.

Atrenta was one of the many companies… Read More