Fast Track your SoC Design

Fast Track your SoC Design
by Paul McLellan on 08-17-2011 at 5:24 pm

Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:

  • finding quality IP faster
  • accelerating IP integration and SoC assembly
  • handing off RTL successfully.
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ANSYS Regional Conference

ANSYS Regional Conference
by Paul McLellan on 08-17-2011 at 3:15 pm

Next Tuesday, August 23rd, is the ANSYS Regional Conference for Silicon Valley. It takes place at the Techmart Network Meeting Center. Apache has three presentations during the day:

  • 9.25-9.45 Andrew Yang Introducing Apache Design Solutions
  • 11.00-11.30 Methodology for delivering power-efficient designs from concept to
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Google buying Motorola

Google buying Motorola
by Paul McLellan on 08-15-2011 at 10:48 am

So Google is buying Motorola Mobility for $12.5B. If you are a partner of Google using Android then this has both upside and downside. The upside is that Motorola, having been in wireless for longer than almost anyone, presumably has a pretty good patent portfolio that can be used to defend against Apple, Nokia, Microsoft et al. The… Read More


ANSYS/Apache

ANSYS/Apache
by Paul McLellan on 08-13-2011 at 2:43 pm

Last week I met with Andrew Yang, erstwhile CEO of Apache Design Systems and now formally President of Apache Design Inc, a wholly owned subsidiary of ANSYS. The merger formally closed at the start of the month. Within ANSYS Apache is positioned as Chip-aware System-level Engineering Simulation. ANSYS is pretty much completely… Read More


Speeding Verification of FPGA Prototype Boards

Speeding Verification of FPGA Prototype Boards
by Paul McLellan on 08-09-2011 at 5:42 pm

It is no secret that SoC designs continue to increase in complexity and time-to-market windows are shrinking. While there is room for debate on just how big a fraction of SoC design effort goes on verification, there is no debating that it is a large part of the total. Simulation is increasingly too slow, especially when software … Read More


Sentinel-PSI Webinar

Sentinel-PSI Webinar
by Paul McLellan on 08-07-2011 at 3:28 pm

The last of the current series of webinars is on Sentinel-PSI,IC-Package, Power and Signal Integrity Solution. It will be at 11am Pacific time on Thursday 11th August. It will be conducted by Dr. Tao Su, product manager of the Sentinel products. Dr. Su has many years of experience in the EDA industry and is specialized in power integrity… Read More


SNUG outside Silicon Valley

SNUG outside Silicon Valley
by Paul McLellan on 08-05-2011 at 6:04 pm

SNUG in Silicon Valley was in March so either you were there or you’ve missed it. But it is the summer (and fall) of SNUG in the rest of the world:

SNUG China (in Beijing, Shanghai, Shenzhen) on August 22nd-30th
SNUG Singapore on August 23rd
SNUG Taiwan (in Hsinchu) on August 25-26th
SNUG Japan (in Tokyo) on September 7th
SNUG … Read More


Assertion-based Formal Verification

Assertion-based Formal Verification
by Paul McLellan on 08-05-2011 at 5:34 pm

Formal verification has grown in importance as designs have grown and it has become necessary to face up to the theoretical impossibility of using simulation to get complete coverage along with the practical impossibility of simulating enough to even get close.

There are a number of solvers for what is called satisfiability (SAT)… Read More


Chip-Package-System Webinar

Chip-Package-System Webinar
by Paul McLellan on 08-05-2011 at 5:14 pm

The webinar on CPS (chip-package-system) is on Tuesday 9th August at 11am Pacific time. It will be conducted by Christopher Ortiz, Principal Application Engineer at Apache Design Solutions. Dr. Ortiz has been with Apache since 2007, supporting the Sentinel product line. Prior to Apache he worked at Agere / LSI, where he investigated… Read More