Imera Virtual Fabric

Imera Virtual Fabric
by Paul McLellan on 01-10-2012 at 6:00 am

Virtual fabric sounds like something that would be good for making the emperor’s new clothes. I talked today to Les Spruiell of Imera to find out what it really is.

Anyone who has worked as either a designer or as an EDA engineer has had the problem of a customer who has a problem but can’t send you the design since it is (a)… Read More


HiFi audio…in all the devices

HiFi audio…in all the devices
by Paul McLellan on 01-09-2012 at 6:00 am

The big challenge with audio is that there are so many standards. Some of this is for historical reasons since audio for mobile (such as mp3), for the home (Dolby 5.1) and for cell-phone voice encoding/decoding have all had very different requirements, different standard setters and so on. But gradually everything is coming together.… Read More


Synopsys, the first 25 years

Synopsys, the first 25 years
by Paul McLellan on 01-08-2012 at 8:00 pm

Synopsys was started in 1986 and so 2011 was its 25th anniversary. They created a little timeline with some of their history. As with most companies, the earlier history is the most interesting, before it was clear what the future would bring. From 1986 to 1990 they grew to $22M in revenue, which was explosive growth. So explosive … Read More


Economist on ARM vs Intel

Economist on ARM vs Intel
by Paul McLellan on 01-06-2012 at 7:16 pm

The Economist has a big article (may need a subscription, can’t tell because I have one, it’s in the print edition too) about ARM versus Intel. It is an interesting read since I think it misses so much of what really drives semiconductor. It tells the story about Intel trying to get into mobile (because it’s main… Read More


VLSI 2012 in Hyderabad

VLSI 2012 in Hyderabad
by Paul McLellan on 01-06-2012 at 3:59 pm

Atrenta will be on a panel session at VLSI 2012 next week in Hyderabad in the center of India. Since I had a development group there over a decade ago this is actually one of the few cities in India that I have visited. Beautiful but very hot at the time I was there.

Atrenta will be represented by Sathyam Pattanam the director of engineering… Read More


T’is the season for…semiconductor forecasts

T’is the season for…semiconductor forecasts
by Paul McLellan on 12-20-2011 at 3:10 pm

T’is the season to be jolly…and to predict the next year’s semiconductor market.

KPMG does a regular survey of senior executives in semiconductor companies to get their outlook on the year ahead. The message this year is mixed. 41% of executives expected their business to grow by more than 5% next year, which sounds not too bad until… Read More


View from the top: Chris Rowen

View from the top: Chris Rowen
by Paul McLellan on 12-20-2011 at 1:41 pm

I met with Chris Rowen, CEO of Tensilica, last week to get his outlook on the year ahead.

He gave me an interesting quote from his time at Silicon Graphics. “We wanted to be very fast in development not to be first to market but so that we could be the last to start.”

A lot of what Tensilica does is bound up with evolving standards in audio,… Read More


View from the top: Ajoy Bose

View from the top: Ajoy Bose
by Paul McLellan on 12-12-2011 at 4:13 pm

I sat down yesterday with Dr. Ajoy Bose, CEO of Atrenta, to get his view of the future of EDA – looking through a high-power “spyglass” of sorts. I first met Ajoy when he was at Software & Technologies. I was then the VP of Engineering for Compass Design Automation and we were considering off-shoring some development. We eventually… Read More


Atrenta’s users. Survey says….

Atrenta’s users. Survey says….
by Paul McLellan on 12-09-2011 at 7:32 pm

Atrenta did an online survey of their users. Of course Atrenta’s users are not necessarily completely representative of the whole marketplace so it is unclear how the results would generalize for the bigger picture, your mileage may vary. About half the people were design engineers, a quarter CAD engineers and the rest … Read More


Challenges in 3D-IC and 2½D Design

Challenges in 3D-IC and 2½D Design
by Paul McLellan on 12-09-2011 at 5:18 pm

3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

The power delivery network is a challenge… Read More