MZ Technologies is a unique company that enables multi-die design by providing critical planning and analysis tools that sit above the traditional EDA design flow. Chip and package design tools are good at what they do. Given a set of constraints, they will deliver a good result. The question is, what is the right set of constraints? … Read More
Author: Mike Gianfagna
MZ Technologies Enables Multi-Die Design with GENIO
Weebit Nano Brings ReRAM Benefits to the Automotive Market
Non-volatile memory (NVM) is a critical building block for most electronic systems. The most popular NVM technology has traditionally been flash. As a discrete part, the technology can be delivered in various form factors. For embedded applications flash presents scaling challenges, however. A new NVM technology developed… Read More
sureCore Enables AI with Ultra-Low Power Memory IP
We all know that AI is becoming pervasive in a wide array of products to make them smarter, safer and feature rich. Just look at the announcements from the recent CES show in Las Vegas to see some examples. These AI workloads demand a lot of compute power. Fueling this trend is the need for significant arrays of embedded memory on chip,… Read More
Synopsys Enhances PPA with Backside Routing
Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side… Read More
Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?
“What you simulate is what you get.” This is the holy grail of many forms of system design. Achieving a high level of accuracy between predicted and actual performance can cut design time way down, resulting in better cost margins, time to market and overall success rates. Achieving a high degree of confidence in predicted performance… Read More
Arteris is Unleashing Innovation by Breaking Down the Memory Wall
There is a lot of discussion about removing barriers to innovation these days. Semiconductor systems are at the heart of unlocking many forms of technical innovation, if only we could address issues such as the slowing of Moore’s Law, reduction of power consumption, enhancement of security and reliability and so on. But there … Read More
How Sarcina Technology Makes Advanced Semiconductor Package Design Easier
For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test … Read More
How MZ Technologies is Making Multi-Die Design a Reality
The next design revolution is clearly upon us. Traditional Moore’s Law is slowing, but the exponential demand for innovation and form factor density is not. When you can no longer get it done with a single monolithic chip, moving to a multi-die approach is the answer. This emerging design methodology has many challenges – supply… Read More
Photonic Computing – Now or Science Fiction?
Cadence recently held an event to dig into the emerging world of photonic computing. Called The Rise of Photonic Computing, it was a two-day event held in San Jose on February 7th and 8th. The first day of the event was also accessible virtually. I attended a panel discussion on the topic – more to come on that. The day delivered a rich… Read More
Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries
The relentless demand for lower power SoCs is evident across many markets. Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost… Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing