The ever-growing demand for longer battery life in mobile devices and energy savings in general have pushed power optimization to the top of designers’ concerns. While various techniques like multi-VT transistors and clock gating offer power savings at gate-level design, the real impact occurs at system level, where hardware… Read More
Author: Lauro Rizzatti
SoC Power Islands Verification with Hardware-assisted Verification
Early SoC Dynamic Power Analysis Needs Hardware Emulation
The relentless pursuit for maximizing performance in semiconductor development is now matched by the crucial need to minimize energy consumption.
Traditional simulation-based power analysis methods face insurmountable challenges to accurately capture complex designs activities in real-world scenarios. As the scale… Read More
Luc Burgun: EDA CEO, Now French Startup Investor
When we last saw Luc Burgun’s name in the semiconductor industry, he was CEO and co-founder of EVE (Emulation and Verification Engineering), creator of the ZeBu (Zero Bugs) hardware emulator. EVE was acquired by Synopsys in 2012.
After the acquisition, Luc moved out of EDA and became an investor. Join me as I catch up with Luc and … Read More
Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge
Two recent software-based algorithmic technologies –– autonomous driving (ADAS/AD) and generative AI (GenAI) –– are keeping the semiconductor engineering community up at night.
While ADAS at Level 2 and Level 3 are on track, AD at Levels 4 and 5 are far from reality, causing a drop in venture capital enthusiasm and money. Today,… Read More
The Corellium Experience Moves to EDA
Bill Neifert invited me to join him on Zoom recently to talk about his move to Corellium, a company known within the DevSecOps (development, security, operations) market. Developers and security groups use its virtualization technology to build, test, and secure mobile and IoT apps, firmware, and hardware.
Not knowing much … Read More
EDA Product Mix Changes as Hardware-Assisted Verification Gains Momentum
The Design Automation Conference, as always, is a good barometer on the state of EDA and my area of interest, verification. The recent DAC offered plenty of opportunities to check on trends and the status quo.
Remarkably, exhibitors and attendees were upbeat about the chip design landscape despite concerns about supply chain … Read More
Meet Kandou’s Frank Lavety, Behind the Scenes Point Person for Timely Product Delivery
I learned about Kandou a year ago and liked what I heard, as should anyone who wants higher res displays and faster downloads from their electronic devices. I’ve been tracking Kandou since and believe it’s living up to its goal to be the undisputed innovator in high-speed, energy-efficient chip-to-chip link solutions to improve… Read More
“Kandou it”
In another departure from my chip design verification “beat,” I took a look at Kandou and like what I learned.
Kandou from Lausanne, Switzerland, boasts “Kandou It” as its tagline and as it should be if Kandou’s USB-C multi-protocol retimer solution with USB4 support is inside next-gen laptops, notebooks, desktops, tablets and… Read More
Software Developers Turn to CacheQ for Multi-Threading CPU Acceleration
Three-year old CacheQ, founded by two former Xilinx executives and a clever group of engineers, produces a distributed heterogenous compute development environment targeting software developers with limited knowledge of hardware architecture.
The promise of compiler tools for heterogeneous compute systems intrigued… Read More
Meeting the Need for Hardware-Assisted Verification
Editor’s Note: Siemens EDA recently introduced a comprehensive hardware-assisted verification system comprised of hardware, software and system verification that streamlines and optimizes verification cycles while helping reduce verification cost. What follows is an edited version of an interview Verification Expert… Read More
Rethinking Multipatterning for 2nm Node