Author: Daniel Payne

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Physical Verification of 3D-IC Designs using TSVs

Physical Verification of 3D-IC Designs using TSVs
by Daniel Payne on 11-12-2011 at 10:36 am
Categories: EDA, Foundries, Siemens EDA, TSMC

3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were… Read More

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SPICE Circuit Simulation at Magma

SPICE Circuit Simulation at Magma
by Daniel Payne on 11-11-2011 at 11:36 am
Categories: Uncategorized
3 Comments

All four of the public EDA companies offer SPICE circuit simulation tools for use by IC designers at the transistor-level, and Magma has been offering two SPICE circuit simulators:

  • FineSIM SPICE (parallel SPICE)
  • FineSIM PRO (accelerated, parallel SPICE)

An early advantage offered by Magma was a SPICE simulator that could be … Read More

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Learning Verilog for ASIC and FPGA Design

Learning Verilog for ASIC and FPGA Design
by Daniel Payne on 11-02-2011 at 11:17 am
Categories: EDA

Verilog History
Prabhu Goel founded Gateway Design Automation and Phil Moorby wrote the Verilog language back in 1984. In 1989 Cadence acquired Gateway and Verilog grew into a de-facto HDL standard. I first met Prabu at Wang Labs in 1982 where I designed a rather untestable custom chip named the WL-2001 (yes, it was named to honor… Read More

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What’s New with Semiconductor Test and Failure Analysis at Mentor?

What’s New with Semiconductor Test and Failure Analysis at Mentor?
by Daniel Payne on 10-28-2011 at 6:03 pm
Categories: EDA, Siemens EDA

ISTFA
Silicon Valley is a great location for trade shows and technical conferences, so if you have an interest in test and failure analysis then don’t miss out on the 37th annual International Symposium for Testing and Failure Analysis. This year ISTFA will be held from Sunday, November 13th thru Thursday, November 17th … Read More

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AMS Design using Dongbu HiTek foundry and Tanner EDA Tools

AMS Design using Dongbu HiTek foundry and Tanner EDA Tools
by Daniel Payne on 10-27-2011 at 12:00 pm
Categories: EDA, Tanner EDA

Every analog designer needs a foundry PDK (Process Design Kits) and EDA tools to design, layout and verify their AMS chip or IP. This week I had a chance to conduct an email interview with Taek-Soo Kim, VP of Technical Engineering at Dongbu HiTek in Korea. This specialty foundry supplies analog silicon worldwide.

Interview
Q: Tell… Read More

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Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 10-20-2011 at 9:56 am
Categories: EDA, Siemens EDA

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow

DRC Wiki

Graphical DRC vs Text-based DRC

Getting Real time Calibre DRC Results with Custom IC Editing

Transistor-level Electrical Rule Checking

Who Needs a 3D Field Solver for IC Design?

Prevention is Better… Read More

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AMS Design at AnSem

AMS Design at AnSem
by Daniel Payne on 10-19-2011 at 3:40 pm
Categories: EDA, Tanner EDA

AnSem has been in the AMS design business since 1998 and uses a variety of commercial EDA tools along with internally developed tools and scripts to automate the process of analog design and technology porting. Their IC designers have completed some 40 AMS projects in diverse areas like:

  • RF CMOS
    • LNA, VCO, Mixers
    • Synthesizers
    • Low-IF/Zero-IF
… Read More
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Mentor at the TSMC Open Innovation Platform Ecosystem Forum

Mentor at the TSMC Open Innovation Platform Ecosystem Forum
by Daniel Payne on 10-17-2011 at 3:14 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.

Tomorrow in San Jose you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.

Here are some of the topics that will interest IC designers… Read More

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EDA and ITC

EDA and ITC
by Daniel Payne on 10-17-2011 at 10:44 am
Categories: EDA, Synopsys

Every SOC that is designed must be tested and the premier conference for test is ITC, held last month in Anaheim, California.

I spoke with Robert Ruiz of Synopsys by phone on September 21st to get an update on what is new with EDA for test engineers this year. Robert and I first met back at Viewlogic when Sunrise was acquired in the 90’s.… Read More

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FPGA Prototyping – What I learned at a Seminar

FPGA Prototyping – What I learned at a Seminar
by Daniel Payne on 10-14-2011 at 10:11 am
Categories: EDA, FPGA, Synopsys

Intro
My first exposure to hardware prototyping was at Intel back in 1980 when the iAPX 432 chip-set group decided to build a TTL-based wire-wrap prototype of a 32 bit processor to execute the Ada language. The effort to create the prototype took much longer than expected and was only functional a few months before silicon came back.… Read More