Mentor at the TSMC Open Innovation Platform Ecosystem Forum

Mentor at the TSMC Open Innovation Platform Ecosystem Forum
by Daniel Payne on 10-17-2011 at 3:14 pm

EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.

Tomorrow in San Jose
you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.

Here are some of the topics that will interest IC designers… Read More


EDA and ITC

EDA and ITC
by Daniel Payne on 10-17-2011 at 10:44 am

Every SOC that is designed must be tested and the premier conference for test is ITC, held last month in Anaheim, California.

I spoke with Robert Ruiz of Synopsys by phone on September 21st to get an update on what is new with EDA for test engineers this year. Robert and I first met back at Viewlogic when Sunrise was acquired in the 90’s.… Read More


FPGA Prototyping – What I learned at a Seminar

FPGA Prototyping – What I learned at a Seminar
by Daniel Payne on 10-14-2011 at 10:11 am

Intro
My first exposure to hardware prototyping was at Intel back in 1980 when the iAPX 432 chip-set group decided to build a TTL-based wire-wrap prototype of a 32 bit processor to execute the Ada language. The effort to create the prototype took much longer than expected and was only functional a few months before silicon came back.… Read More


How ST-Ericsson Improved DFM Closure using SmartFill

How ST-Ericsson Improved DFM Closure using SmartFill
by Daniel Payne on 10-07-2011 at 2:38 pm

DFM closure is a growing issue these days even at the 45nm node, and IC designers at ST-Ericsson have learned that transitioning from dummy fill to SmartFill has saved them time and improved their DFM score.

The SOC
ST-Ericsson designed an SOC for mobile platforms called the U8500 and their foundry choice was a 45nm node at STMicroelectronicsRead More


Circuit Simulation and Ultra low-power IC Design at Toumaz

Circuit Simulation and Ultra low-power IC Design at Toumaz
by Daniel Payne on 10-06-2011 at 4:31 pm

I read about how Toumaz used the Analog Fast SPICE (AFS) tool from BDA and it sounded interesting so I setup a Skype call with Alan Wong in the UK last month to find out how they design their ultra low-power IC chips.


Interview

Q: Tell me about your IC design background.
A: I’ve been at Toumaz almost 8 years now and before that at Sony… Read More


Memory Cell Characterization with a Fast 3D Field Solver

Memory Cell Characterization with a Fast 3D Field Solver
by Daniel Payne on 09-29-2011 at 12:07 pm

Memory designers need to predict the timing, current and power of their designs with high accuracy before tape-out to ensure that all the design goals will be met. Extracting the parasitic values from the IC layout and then running circuit simulation is a trusted methodology however the accuracy of the results ultimately depend… Read More


Analog IP Design at Moortec

Analog IP Design at Moortec
by Daniel Payne on 09-28-2011 at 12:34 pm

Stephen Crosher started up Moortec in the UK back in 2005 with the help of his former Zarlink co-workers and they set to work offering AMS design services and eventually created their own Analog IP like the temperature sensor shown below:

We spoke by phone last week about his start-up experience and how they approach AMS design.… Read More


A Verilog Simulator Comparison

A Verilog Simulator Comparison
by Daniel Payne on 09-22-2011 at 2:40 pm

Intro
Mentor, Cadence and Synopsys all offer Verilog simulators, however when was the last time that you benchmarked your simulator against a tool from a smaller company?

I just heard from an RTL designer (who wants to remain anonymous) about his experience comparing a Verilog simulator called CVC from Tachyon against ModelSim… Read More


AMS Design, Optimization and Porting

AMS Design, Optimization and Porting
by Daniel Payne on 09-19-2011 at 2:35 pm

AMS design flows can follow a traditional path or consider trying something new. The traditional path goes along the following steps:
[LIST=1]

  • Design requirements
  • Try a transistor-level schematic
  • Run circuit simulation
  • Compare the simulated results versus the requirements, re-size the transistors and go back to step 3 or
  • Read More

    Tanner EDA Newsletter – Fall 2011

    Tanner EDA Newsletter – Fall 2011
    by Daniel Payne on 09-15-2011 at 10:47 am

    logo top

    From the President: Another Great YearThanks to innovative, cost-effective technology and excellence in customer support, we’ve just ended fiscal year 2011 (on May 31st) with solid growth. Revenue was up 8%, we added 139 new customers, and we’re continuing to reach out to technology partners for MEMS and for the analog and mixed-signalRead More