Digital IC design gets a lot of attention, because all of our modern devices primarily use digital logic, but in reality whenever you have a sensor like a camera, accelerometer, gyroscope or any radio like Bluetooth, WiFi or NFC, then you’re really in the realm of analog, and that’s where mixed-signal IC design comes… Read More
Author: Daniel Payne
Using Machine Learning to Improve EDA Tool Flow Results
Back in 2020 I first learned from Synopsys about how they had engineered a better way to do optimize layouts on digital designs by using machine learning techniques, instead of relying upon manual approaches. The product was named DSO.ai, standing for Design Space Optimization, and it produced a more optimal floor-plan in less… Read More
SoC Vulnerabilities
As I read both the popular and technical press each week I often see articles about computer systems being hacked, and here’s just a few vulnerabilities from this week:
- Global phone hacks expose darker side of Israel’s startup nation image
- How Taiwan is trying to defend against a cyber World War III
- Kaseya receives
Automotive Safety Island: Test, Safety, Security, ISO 26262
I first fell in love with electric vehicles back in 1978 as an Electrical Engineering student, studying at the University of Minnesota. What caught my fancy was a small advertisement listed in the back of Popular Mechanics magazine to build your own electric vehicle by replacing the gas engine of a Honda with an electric motor, so… Read More
Webinar: Learn about NVMe conformance Testing
Several years ago I recall upgrading my aging MacBook Pro laptop from using a Hard Disk Drive (HDD) to a Solid State Drive (SSD) that used Non-Volatile Memory (NVM). Oh what a speed improvement when pushing that On button each morning to start the work day, or clicking an App to see it launch without delay. Another epiphany for me in … Read More
Circuit Simulation Challenges to Design the Xilinx Versal ACAP
One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals… Read More
EDA Design and Amazon Web Services (AWS)
I first remember blogging about EDA in the cloud starting back in 2011, so what’s changed in the last 10 years you may ask? In 2011, it was basically a handful of EDA point tools running batch mode in the cloud, and you were on your own to integrate those into a coherent flow, so expect help from the CAD and IT departments for sure.… Read More
Speed Up LEF Generation Times on Huge IC Designs
For IC designs there are many data formats used throughout the logical and physical design process, and one of those file formats is called LEF, an acronym for Library Exchange Format, created by Tangent, an early EDA company with Place and Route tools that was acquired by Cadence way back in March 1989. LEF generation times can become… Read More
Cadence adds a new Fast SPICE Circuit Simulator
In the early years of Cadence their growth was bolstered through many well-timed acquisitions, however over the last several years I’ve noticed a distinctively different trend where they have internally developed EDA tools. I had a Zoom call with Jay Madiraju from Cadence, who markets their newly announced Fast SPICE … Read More
From Silicon To Systems
The annual Siemens Digital Industries Software user group event was held virtually on May 26th, which made it easy to attend from my home office, although selecting from the list of speakers was a challenge, because they offered 475 sessions, wow. My focus is EDA, so I listened to Joseph Sawicki, the Executive Vice President, IC … Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay