Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
by Daniel Payne on 01-02-2022 at 10:00 am

circuit sizing min

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness times have changed, and circuit designers can work smarter … Read More


DAC 2021 – Cliosoft Overview

DAC 2021 – Cliosoft Overview
by Daniel Payne on 12-30-2021 at 6:00 am

Simon and Karim min

It’s been awhile since I really looked at what Cliosoft has to offer in the EDA tool space, so at the 58th DAC I stopped by their exhibit booth on Tuesday to visit with Karim Khalfan, VP of Application Engineering, and Simon Rance, VP of Marketing. Their booth had all of the hot market segments listed: Automotive, 5G, IoT, AI, … Read More


DAC 2021 – Taming Process Variability in Semiconductor IP

DAC 2021 – Taming Process Variability in Semiconductor IP
by Daniel Payne on 12-27-2021 at 10:00 am

process node variability min

Tuesday at DAC was actually my very first time attending a technical session, and the presentation from Nebabie Kebebew, Siemens EDA, was called, Mitigating Variability Challenges of IPs for Robust Designs. There were three presentations scheduled for that particular Designer, IP and Embedded Systems track, but with the COVID… Read More


DAC 2021 – Siemens EDA talks about using the Cloud

DAC 2021 – Siemens EDA talks about using the Cloud
by Daniel Payne on 12-21-2021 at 10:00 am

Craig Johnson

My third event at DAC on Monday was all about using EDA tools in the Cloud, and so I listened to Craig Johnson, VP EDA Cloud Solutions, Siemens EDA. Early in the day I heard from Joe Sawicki, Siemens EDA, on the topic of Digitalization.

Why even use the Cloud for EDA? That’s a fair question to ask, and Craig had several high-level… Read More


DAC 2021 – Accellera Panel all about Functional Safety Standards

DAC 2021 – Accellera Panel all about Functional Safety Standards
by Daniel Payne on 12-14-2021 at 10:00 am

FS data format min

Functional safety has been at the forefront of the electrification of our vehicles with new ADAS features, and the push to reach autonomous driving, while having compliance with the ISO 26262 functional safety standard. I attended the Accellera hosted panel discussion on Monday at DAC, hearing from functional safety panelists… Read More


DAC 2021 – Joe Sawicki explains Digitalization

DAC 2021 – Joe Sawicki explains Digitalization
by Daniel Payne on 12-13-2021 at 10:00 am

semiconductor content min

Monday at DAC this year started off on a very optimistic note as Joe Sawicki from Siemens EDA presented in the Pavilion on the topic of Digitalization, a frequent theme in the popular press because of the whole Work From Home transition that we’ve gone through during the pandemic. Several industries are benefiting from the… Read More


System Technology Co-Optimization (STCO)

System Technology Co-Optimization (STCO)
by Daniel Payne on 11-30-2021 at 10:00 am

An early package prototype

My first exposure to seeing multiple die inside of a single package in order to get greater storage was way back in 1978 at Intel, when they combined two 4K bit DRAM die in one package, creating an 8K DRAM chip, called the 2109. Even Apple used two 16K bit DRAM chips from Mostek to form a 32K bit DRAM, included in the Apple III computer, circa… Read More


Machine Learning Applied to IP Validation, Running on AWS Graviton2

Machine Learning Applied to IP Validation, Running on AWS Graviton2
by Daniel Payne on 11-22-2021 at 10:00 am

Solido Variation Designer on Neoverse N1 CPU min

I recall meeting with Solido at DAC back in 2009, learning about their Variation Designer tool that allowed circuit designers to quickly find out how their designs performed under the effects of process variation, in effect finding the true corners of the process. Under the hood the Solido tool was using Machine Learning (ML) techniques… Read More


Synopsys Expands into Silicon Lifecycle Management

Synopsys Expands into Silicon Lifecycle Management
by Daniel Payne on 11-18-2021 at 10:00 am

SLM, Synopsys

I spoke with Steve Pateras of Synopsys last week to better understand what was happening with their Silicon Lifecycle Management vision, and I was reminded of a Forbes article from last year: Never Heard of Silicon Lifecycle Management? Join the Club. At least two major EDA vendors are now using the relatively new acronym SLM, and… Read More


Webinar: Boosting Analog IC Layout Productivity

Webinar: Boosting Analog IC Layout Productivity
by Daniel Payne on 11-09-2021 at 10:00 am

Animate Preview

Digital IC designers use a well-known methodology with pre-designed standard cells and other IP blocks playing a major re-use role, however in the analog IC design world there are more nuanced requirements which often dictate that a new analog block be highly customized. The downside is that customizing analog IC layout takes… Read More